Loading...
Bus Operation
7-10
M68060 USER’S MANUAL
MOTOROLA
Figure 7-9 illustrates the transfer of a long-word operand from an odd address requiring
more than one bus cycle. For the first transfer or bus cycle, the SIZx signals specify a byte
transfer, and the byte offset is $1. The slave device supplies the byte and acknowledges the
data transfer. When the processor starts the second cycle, the SIZx signals specify a word
transfer with a byte offset of $2. The next two bytes are transferred during this cycle. The
processor then initiates the third cycle, with the SIZx signals indicating a byte transfer. The
byte offset is now $0; the port supplies the final byte and the operation is complete. This
example is similar to the one illustrated in Figure 7-10 except that the operand is word sized
and the transfer requires only two bus cycles. Figure 7-11 illustrates a functional timing dia-
gram for a misaligned long-word read transfer.
Figure 7-9. Example of a Misaligned Long-Word Transfer
Figure 7-10. Example of Misaligned Word Transfer
DATA BUS
31 0
X OP0 X X
XX OP1 OP2
OP3 XX X
MEMORY
31 0
XXX OP0 OP1 OP2
OP3 XXX XXX XXX
TRANSFER 1
TRANSFER 2
TRANSFER 3
24 23 16 15 8 7
24 23 16 15 8 7
REGISTER
31 0
OP0 OP1 OP2 OP3
24 23 16 15 8 7
MOVE.L D0,$XXXXXXX1
DATA BUS
31 0
— OP2
OP3 ———
MEMORY
31 0
XXX XXX XXX OP2
OP3 XXX XXX XXX
TRANSFER 1
TRANSFER 2
24 23 16 15 8 7
24 23 16 15 8 7
Register
31 0
OP2 OP3
24 23 16 15 8 7
MOVE.W D0,$XXXXXXX3
Loading...
Terms of Use | Privacy Policy | DMCA Policy
2006-2020 Rsmanuals.com