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Bus Operation
MOTOROLA
M68060 USER’S MANUAL
7-9
7.6 MISALIGNED OPERANDS
All MC68060 data formats can be located in memory on any byte boundary. A byte operand
is properly aligned at any address, a word operand is misaligned at an odd address, and a
long word is misaligned at an address that is not evenly divisible by four. However, since
operands can reside at any byte boundary, they can be misaligned. Although the MC68060
does not enforce any alignment restrictions for data operands (including program counter
(PC) relative data addressing), some performance degradation occurs when additional bus
cycles are required for long-word or word operands that are misaligned. For maximum per-
formance, data items should be aligned on their natural boundaries. All instruction words
and extension words must reside on word boundaries. Attempting to prefetch an instruction
word at an odd address causes an address error exception. Refer to
Section 8 Exception
Processing
for details on address error exceptions.
The MC68060 data memory unit converts misaligned operand accesses that are noncach-
able to a sequence of aligned accesses. These aligned accesses are then sent to the bus
controller for completion, always resulting in aligned bus transfers. Misaligned operand
accesses that miss in the data cache are cachable and are not aligned before line filling.
Refer to
Section 5 Caches
for details on line fill and the data cache.
Table 7-2. Summary of Access Types vs. Bus Signal Encoding
Bus
Signal
Data
Cache
Push
Access
Normal
Data/
Code
Access
Table
Search
Access
MOVE16
Access
Alternate
Access
Interrupt
Acknowledge
LPSTOP
Broadcast
Cycle
Breakpoint
Acknowledge
A31–A0 Access
Address Access
Address Entry
Address Access
Address Access
Address $FFFFFFFF $FFFFFFFE $00000000
UPA1,
UPA0 $0 MMU
Source1$0 MMU
Source1$0 $0 $0 $0
SIZ1,
SIZ0 L/Line B/W/L/Line Long Word Line B/W/L Byte Word Byte
TT1, TT0 $0 $0 $0 $1 $2 $3 $3 $3
TM2–
TM0 $0 $1,2,5, or 6 $3 or 4 $1 or 5
Function
Code=0,3,
4,7
Debug
Access=
1,5,6
Int. Level $1–7 $0 $0
TLN1,
TLN0 Cache Set
Entry
Cache Set
Entry2Undefined Undefined Undefined Undefined Undefined Undefined
R/W Write Read/Write Read/Write Read/Write Read/Write Read Write Read
LOCK
LOCKE Negated Asserted/
Negated3Asserted/
Negated3Negated Negated Negated Negated Negated
CIOUT Negated MMU
Source1Negated MMU
Source1Asserted Negated Negated Negated
NOTES
1) The UPA1, UPA0, and
CIOUT
signals are determined by the U1, U0, and CM bit fields, respectively,
corresponding to the access address.
2) The TLNx signals are defined only for normal push accesses and normal data line read accesses.
3) The
LOCK
signal is asserted during TAS and CAS operand accesses and for some table search update
sequences.
LOCKE
is asserted for the last bus cycle of a locked sequence of bus cycles.
LOCK
and
LOCKE
may also be asserted after the execution of a MOVEC instruction that sets the L or LE bit, respectively, in the
BUSCR (see
7.4 Bus Control Register
).
4) Refer to
Section 2 Signal Description
for definitions of the TMx signal encoding for normal, MOVE16, and
alternate accesses.
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