Loading...
Bus Operation
7-6
M68060 USER’S MANUAL
MOTOROLA
bidirectionally with 32-, 16-, or 8-bit peripherals and memories. It dynamically recognizes the
size of the selected peripheral or memory device and then reads or writes the appropriate
data from that location. Refer to MC68150/D,
MC68150 Dynamic Bus Sizer
, for information
on this device.
Blocks of memory that must be contiguous, such as for code storage or program stacks,
must be 32 bits wide. Byte- and word-sized I/O ports that return an interrupt vector during
interrupt acknowledge cycles must be mapped into the low-order 8 or 16 bits, respectively,
of the data bus.
The multiplexer takes the four bytes of a long-word transfer and routes them to their required
positions. For example, OP0 would normally be routed to D31–D24 on an aligned long-word
transfer, but it can also be routed to any other byte position supporting a misaligned data
transfer. The same is true for any of the other operand bytes. The transfer size (SIZ0 and
SIZ1) and byte offset (A1 and A0) signals determine the positioning of the bytes (see Table
7-1) or alternatively, BS3–BS0 may be used instead of SIZx, A1, and A0. The BSx pins
determine which byte sections are active. The size indicated on the SIZx signals corre-
sponds to the size of the operand transfer for the entire bus cycle (except for burst-inhibited
bus cycles). During an operand transfer, A31–A2 indicate the long-word base address for
the first byte of the operand to be accessed; A1 and A0 indicate the byte offset from the
base. For long-word or line bus cycles, external logic must ignore address bits A1 and A0
for proper operation.
Figure 7-7. Data Multiplexing
REGISTER
ADDRESS
$xxxxxxx0
EXTERNAL
DATA BUS
31 024 23 16 15 8 7
OP0 OP1 OP2 OP3
ROUTING
MULTIPLEXER
31 024 23 16 15 8 7
EXTERNAL BUS
INTERNAL TO
THE MC68060
BS0 BS1 BS2 BS3
D31–D24 D23–D16 D15–D8 D7–D0
Loading...
Terms of Use | Privacy Policy | DMCA Policy
2006-2020 Rsmanuals.com