M68060 USER’S MANUAL
LE—Lock End Bit
0 = Negate external LOCKE signal.
1 = Assert external LOCKE signal.
SLE—Shadow Copy, Lock End Bit
0 = LOCKE asserted at time of exception.
1 = LOCKE negated at time of exception.
The external LOCK signal is asserted starting with the assertion of TS for the bus cycle of
the next operand read or write after setting the L-bit in the BUSCR. The external LOCKE
signal is asserted starting with the assertion of TS for the bus cycle of the next operand write
after setting the LE bit in the BUSCR. Both the LOCK and LOCKE external signals are
negated the cycle after the final TA assertion associated with the TS that asserted LOCKE.
The final operand write cycle must not be misaligned. A final write to the BUSCR must be
made in order to clear the L and LE bits even though the external signals have already
negated. The L and LE bits are cleared when the processor is reset.
The SL and SLE bits in the BUSCR are provided to retain a copy of the L and LE bits at the
time of an exception. When an exception occurs, the MC68060 copies the L and LE bits to
the SL and SLE bits respectively, negates the external LOCK and LOCKE pins, and clears
the L and LE bits. It is recommended that all interrupts be masked prior to the use of BUSCR.
If the cause of the exception is an access error, a bit in the fault status long word (FSLW) in
the access error frame is used to signify that a locked sequence was being executed at the
time of the fault.
7.5 DATA TRANSFER MECHANISM
Figure 7-6 illustrates how the bus designates operands for transfers on a byte boundary sys-
tem. The integer unit handles floating-point operands as a sequence of related long-word
operands. These designations are used in the figures and descriptions that follow.
Figure 7-7 illustrates general multiplexing between an internal register and the external bus.
The internal register connects to the external data bus through the internal data bus and
multiplexer. The data multiplexer establishes the necessary connections for different com-
binations of address and data sizes.
Unlike the MC68020 and MC68030 processors, the MC68060 does not support dynamic
bus sizing and expects the referenced device to accept the requested access width. The
MC68150 dynamic bus sizer is designed to allow the 32-bit MC68060 bus to communicate
Figure 7-6. Internal Operand Representation
OP1 OP2 OP3