M68060 USER’S MANUAL
7.2 FULL-, HALF-, AND QUARTER-SPEED BUS OPERATION AND BCLK
To simplify the description of full-, half-, and quarter-speed bus operation, the term “bus
clock” or “BCLK” is introduced to describe the effective frequency of bus operation. The bus
clock is analogous to the MC68040 clock input called BCLK. The MC68040 BCLK defines
when input signals are sampled and when output signals begin to transition. Once the rela-
tionship of CLK, CLKEN, and the virtual BCLK is established, it is possible to describe the
MC68060 bus more easily, relative to BCLK.
CLKEN allows the bus to synchronize to BCLK which is running at half or quarter speed of
the processor clock (CLK). On rising CLK edges in which CLKEN is asserted, inputs to the
processor are recognized and outputs of the processor may begin to assert, negate, or
three-state. On rising CLK edges in which CLKEN is negated, no inputs are recognized and
no outputs begin to change (except BB and TIP). Figure 7-1 illustrates the general relation-
ship between CLK, CLKEN, and most input and output signals.
For brevity, the term “full-speed bus” is introduced to refer to systems in which BCLK is run-
ning at the same frequency as CLK. The term “half-speed bus” refers to systems in which
BCLK is running at half the frequency of CLK. For those familiar with the MC68040, the half-
speed bus is analogous to the MC68040 implementation. The term “quarter-speed bus”
refers to systems in which BCLK is running at one quarter the frequency of CLK. The
MC68060 clocking mechanism is designed so that systems designed today can be
upgraded with higher-frequency MC68060s, without forcing the rest of the system to operate
at the same higher processor frequency. This flexibility also allows the MC68060 to be used
in existing MC68040 system designs.
A full-speed bus design is achieved by continuously asserting CLKEN as shown in Figure
7-2. A half speed bus is achieved by asserting CLKEN about every other rising edge of CLK.
Figure 7-3 shows a timing diagram of the relationship between CLK, CLKEN, and BCLK for
half-speed bus operation. A quarter-speed bus is achieved by asserting CLKEN once about
every four rising edges of CLK. Figure 7-4 shows a timing diagram of the relationship
between CLK, CLKEN, and BCLK for quarter-speed bus operation.
Note that once BCLK has been established, inputs and outputs appear to be synchronized
to this virtual BCLK. To simplify the description of MC68060 bus operation, the rising edges
Figure 7-4. Quarter-Speed Clock
BB or TIP