The MC68060 bus interface supports synchronous data transfers between the processor
and other devices in the system. This section provides a functional description of the bus,
the signals that control the bus, and the bus cycles provided for data transfer operations.
Operation of the bus is defined for transfers initiated by the processor as a bus master and
for transfers initiated by an alternate bus master which the processor snoops as a slave
device. Descriptions of the error and halt conditions, bus arbitration, and the reset operation
are also included. For timing specifications, refer to
Section 12 Electrical and Thermal
The MC68060 uses the address bus (A31A0) to specify the address for a data transfer and
the data bus (D31–D0) to transfer the data. Control and attribute signals indicate the begin-
ning and type of a bus cycle as well as the address space and size of the transfer. The
selected device then controls the length of the cycle by terminating it using the control sig-
The MC68060 CLK is distributed internally to provide logic timing. CLKEN indicates impor-
tant rising CLK edges for the bus interface controller but does not directly affect internal
operation or timing of the MC68060. Its main purpose is to allow for easier system design.
CLKEN makes possible full-, half-, and quarter-speed bus operation by providing a signal to
qualify valid rising CLK edges. In general, on rising CLK edges in which CLKEN is asserted,
inputs are sampled and outputs begin to change. However, there are some inputs that are
sampled and outputs that transition on rising CLK edges when CLKEN is negated.
Inputs to the MC68060 (other than the IPLx and RSTI signals) are synchronously sampled
and must be stable during the sample window defined by t
and t
(see Figure 7-1) to guar-
antee proper operation. The asynchronous IPLx and RSTI signals are sampled on the rising
edge of CLK, but are internally synchronized to resolve the input to a valid level before being
used. Since the timing specifications for the MC68060 are referenced to the rising edge of
CLK, they are valid only for the specified operating frequency and must be scaled for lower
operating frequencies.
Outputs to the MC68060 begin to transition on rising CLK edges in which CLKEN is
asserted. However, when BB and TIP transition from being asserted to being three-stated,
they are driven negated for one CLK before they are three-stated. Refer to Figure 7-2, Fig-
ure 7-3, and Figure 7-4 for an illustration. Furthermore, the processor status signals (PSTx),
RSTO, and IPEND output signals are updated on rising edges of CLK regardless of the
CLKEN input.
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