Floating-Point Unit
FPCR exception enable byte is set and the corresponding INEX bit in the FPSR EXC byte
is also set). TRAP DISABLED RESULTS (FPCR OVFL BIT CLEARED). The values defined
in Table 6-13 are stored in the destination based on the rounding mode defined in the FPCR
MODE byte. The result is rounded according to the rounding precision defined in the FPCR
MODE byte if the destination is a floating-point data register. If the destination is in memory
or an integer data register, then the rounding precision in the FPCR MODE byte is ignored,
and the given destination format defines the rounding precision. If the instruction has a
forced rounding precision (e.g., FSADD, FDMUL), the instruction defines the rounding pre-
cision. TRAP ENABLED RESULTS (FPCR OVFL BIT SET). The result stored in the des-
tination is the same as the result stored when the trap is disabled before control is passed
to the user OVFL handler. For an FMOVE OUT instruction, the operand is stored in memory
or integer data register, and then control is passed to the user OVFL handler as a post-
instruction exception. If the destination is a floating-point data register, control is passed to
the user OVFL handler as a pre-instruction exception when the next floating-point operation
is encountered.
The user OVFL handler must execute an FSAVE instruction as the first floating-point instruc-
tion to prevent further exceptions from being taken. The address of the instruction that
causes the overflow is available to the user OVFL handler in the FPIAR. By examining the
instruction, the user OVFL handler can determine the arithmetic operation type and destina-
tion location. The exception operand is stored in the floating-point state frame (generated by
the FSAVE). When an overflow occurs, the exception operand is defined differently for var-
ious destination types:
1. FMOVE OUT instruction (memory or integer data register destination)—the value in
the exception operand is the intermediate result mantissa rounded to the destination
precision, with a 15-bit exponent biased as a normal extended-precision number. In
the case of a memory destination, the evaluated effective address of the operand is
available in the integer stack frame format $3. This allows the user OVFL handler to
overwrite the default result, if necessary, without recalculating the effective address.
2. Floating-point data register destination—the value in the exception operand is the in-
termediate result rounded to extended precision, with an exponent bias of $3FFF–
$6000 rather than $3FFF. The additional bias of –$6000 is used so that it is possible
to represent the larger exponent in a 15-bit format.
In addition to normal overflow, the exponential instructions (ex, 10x, 2x, SINH, COSH, and
FSCALE) may generate results that grossly overflow the 16-bit exponent of the internal
Table 6-13. Overflow Rounding Mode Values
Rounding Mode Result
RN Infinity, with the sign of the intermediate result.
RZ Largest magnitude number, with the sign of the intermediate result.
RM For positive overflow, largest positive number; for negative overflow, – infinity.
RP For positive overflow, + infinity; for negative overflow, largest negative number.
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