Floating-Point Unit
the user OPERR handler, as a post-instruction exception. If desired, the user OPERR han-
dler can overwrite the default result.
If the destination is a floating-point data register, the register is not modified. Control is
passed to the user OPERR handler as a pre-instruction exception when the next floating-
point instruction is encountered. In this case, the user OPERR handler should generate the
appropriate result.
The OPERR user handler must execute an FSAVE instruction as the first floating-point
instruction to prevent the FPU from taking more exceptions. The FSAVE frame generates a
floating-point frame that contains the source operand that has been converted to extended
precision. If the destination is a floating-point data register, the register contains the original,
unmodified value. The FPIAR points to the floating-point instruction that caused the excep-
tion. In addition, if the offending instruction is an FMOVE OUT, an integer stack frame format
$3 is created as a result of a post-instruction exception, the effective address of the desti-
nation memory operand is provided. The effective address field is undefined if the destina-
tion is an integer data register.
The user OPERR exception handler may discard the floating-point state frame once the
handler has completed. The RTE instruction must be executed to return to normal instruc-
tion flow.
6.6.4 Overflow
An overflow exception is detected for arithmetic operations in which the destination is a float-
ing-point data register or memory when the intermediate result’s exponent is greater than or
equal to the maximum exponent value of the selected rounding precision. Overflow can only
occur when the destination is in the S-, D-, or X-precision format; all other data format over-
flows are handled as operand errors. At the end of any operation that could potentially over-
flow, the intermediate result is checked for underflow, rounded, and then checked for
overflow before it is stored to the destination. If overflow occurs, the OVFL bit is set in the
FPSR EXC byte.
Even if the intermediate result is small enough to be represented as an extended-precision
number, an overflow can occur. The intermediate result is rounded to the selected precision,
and the rounded result is stored in the extended-precision format. If the magnitude of the
intermediate result exceeds the range of the selected rounding precision format, an overflow
The MC68060 is implemented such that when the OVFL bit is set in the FPSR EXC byte as
a result of a floating-point instruction, the processor always takes a nonmaskable overflow
exception. If the destination is a floating-point data register, then the register is not affected,
and a pre-instruction exception is reported. If the destination is a memory or integer data
register, an undefined result is stored, and a post-instruction exception is taken immediately.
Execution begins at the M68060SP OVFL exception handler to provide MC68881-compat-
ible operation. The M68060SP then determines whether or not control is passed back to nor-
mal instruction flow (the OVFL bit in the FPCR exception enable byte is cleared), to the user
OVFL handler (the OVFL bit in the FPCR exception enable byte is set), or to the user INEX
handler (the OVFL bit in the FPCR exception enable byte is cleared, but the INEX bit in the
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