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Floating-Point Unit
MOTOROLA M68060 USER’S MANUAL 6-25
The user BSUN exception handler must execute an FSAVE as its first floating-point instruc-
tion. FSAVE allows other floating-point instructions to execute without reporting the BSUN
exception again, although none of the state frame values are useful in the execution of the
user BSUN exception handler. The BSUN exception is unique in that the exception is taken
before the conditional predicate is evaluated. If the user BSUN exception handler does not
set the PC to the instruction following the one that caused BSUN exception when returning,
the exception is executed again. Therefore, it is the responsibility of the user BSUN excep-
tion handler to prevent the conditional instruction from taking the BSUN exception again.
There are four ways to prevent taking the exception again:
1. Incrementing the stored PC in the stack bypasses the conditional instruction. This
technique applies to situations where a fall-through is desired. Note that accurate cal-
culation of the PC increment requires detailed knowledge of the size of the conditional
instruction being bypassed.
2. Clearing the NAN bit prevents the exception from being taken again. However, this
alone cannot deterministically control the result’s indication (true or false) that would
be returned when the conditional instruction re-executes.
3. Disabling the BSUN bit also prevents the exception from being taken again. Like the
second method, this method cannot control the result indication (true or false) that
would be returned when the conditional instruction re-executes.
4. Examining the conditional predicate and setting the FPCC NAN bit accordingly pre-
vents the exception from being taken again. This technique gives the most control
since it is possible to predetermine the direction of program flow. Bit 7 of the F-line op-
eration word indicates where the conditional predicate is located. If bit 7 is set, the con-
ditional predicate is the lower six bits of the F-line operation word. Otherwise, the
conditional predicate is the lower six bits of the instruction word, which immediately fol-
lows the F-line operation word. Using the conditional predicate and the table for IEEE
nonaware test in 6.4.2 Conditional Testing, the condition codes can be set to return
a known result indication when the conditional instruction is re-executed.
Prior to exiting the user BSUN exception handler, the user exception handler discards the
floating-point state frame before executing the RTE to return to normal program flow.
6.6.2 Signaling Not-a-Number (SNAN)
An SNAN is used as an escape mechanism for a user-defined, non-IEEE data type. The pro-
cessor never creates an SNAN as a result of an operation; a NAN created by an operand
error exception is always a nonsignaling NAN. When an operand is an SNAN involved in an
arithmetic instruction, the SNAN bit is set in the FPSR EXC byte. Since the FMOVEM,
FMOVE FPCR, and FSAVE instructions do not modify the status bits, they cannot generate
exceptions. Therefore, these instructions are useful for manipulating SNANs.
6.6.2.1 TRAP DISABLED RESULTS (FPCR SNAN BIT CLEARED). If the destination
data format is S, D, X, or P, then the most significant bit of the fraction is set to one and the
resulting nonsignaling NAN is transferred to the destination. No bits other than the SNAN bit
of the NAN are modified, although the input NAN is truncated if necessary. If the destination
data format is B, W, or L, then the 8, 16, or 32 most significant bits of the SNAN significand,
with the SNAN bit set, are written to the destination.
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