6-24 M68060 USER’S MANUAL MOTOROLA
type exception. The M68060SP passes control over to the user-supplied exception handler,
A single instruction execution can generate multiple exceptions. When multiple exceptions
occur with exceptions enabled for more than one exception class, the highest priority excep-
tion is reported; the lower priority exceptions are never reported or taken. The previous list
of arithmetic floating-point exceptions is in order of priority. The bits of the ENABLE byte are
organized in decreasing priority, with bit 15 being the highest and bit 8 the lowest. The ex-
ception handler must check for multiple exceptions. The address of the exception handler is
derived from the vector number corresponding to the exception. The following is a list of mul-
tiple instruction exceptions that can occur:
• SNAN and INEX1
• OPERR and INEX2
• OPERR and INEX1
• OVFL and INEX2 and/or INEX1
• UNFL and INEX2 and/or INEX1
• INEX2 and INEX1
6.6.1 Branch/Set on Unordered (BSUN)
The BSUN exception is the result of performing an IEEE nonaware conditional test associ-
ated with the FBcc, FDBcc, FTRAPcc, and FScc instructions when an unordered condition
is present. Refer to 6.4.2 Conditional Testing for information on conditional tests.
If a floating-point exception is pending from a previous floating-point instruction, a pre-
instruction exception is taken to handle that exception. After the appropriate exception han-
dler is executed, the conditional instruction is restarted. When the previous floating-point
instruction has completed including related exception handling, the conditional predicate is
evaluated and checked for a BSUN exception before executing the conditional instruction.
A BSUN exception is generated in hardware through the FBcc instruction only. All other
BSUN-generating instructions (FDBcc, FTRAPcc, and FScc) are emulated via the
M68060SP. No M68060SP BSUN handler is provided since the processor already provides
MC68881-compatible operation when reporting a BSUN exception.
A BSUN exception occurs if the conditional predicate is one of the IEEE nonaware branches
and the FPCC NAN bit is set. When this condition is detected, the BSUN bit in the FPSR
EXC byte is set.
220.127.116.11 TRAP DISABLED RESULTS (FPCR BSUN BIT CLEARED). The floating-point
condition is evaluated as if it were the equivalent IEEE aware conditional predicate. No
exceptions are taken.
18.104.22.168 TRAP ENABLED RESULTS (FPCR BSUN BIT SET). The processor takes a float-
ing-point pre-instruction exception. A $0 stack frame is saved, and vector number 48 is gen-
erated to access the BSUN exception vector. The BSUN entry in the processor’s vector
table points to the user BSUN exception handler.