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Floating-Point Unit
6-16 M68060 USER’S MANUAL MOTOROLA
If no underflow occurs, the intermediate result is rounded according to the user-selected
rounding precision and rounding mode. After rounding, the INEX2 bit of the FPSR EXC byte
is set accordingly. Finally, the magnitude of the result is checked to see if it is too large to
be represented in the current rounding precision. If so, the OVFL bit of the FPSR EXC byte
is set, and the MC68060 takes a nonmaskable overflow exception and executes the
M68060SP overflow exception handler. The M68060SP returns a correctly signed infinity or
a correctly signed largest normalized number, depending on the rounding mode in effect.
6.4.2 Conditional Testing
Unlike the integer arithmetic condition codes, an instruction either always sets the floating-
point condition codes in the same way or it does not change them at all. Therefore, the
instruction descriptions do not include floating-point condition code settings. The following
paragraphs describe how floating-point condition codes are set for all instructions that mod-
ify condition codes. Refer to 6.1.3.1 Floating-Point Condition Code Byte for a description
of the FPCC byte.
The data type of the operation’s result determines how the four condition code bits are set.
Table 6-8 lists the condition code bit setting for each data type. The MC68060 generates
only eight of the 16 possible combinations. Loading the FPCC with one of the other combi-
nations and executing a conditional instruction can produce an unexpected branch condi-
tion.
The inclusion of the NAN data type in the IEEE floating-point number system requires each
conditional test to include the NAN condition code bit in its Boolean equation. Because a
comparison of a NAN with any other data type is unordered (i.e., it is impossible to determine
if a NAN is bigger or smaller than an in-range number), the compare instruction sets the
NAN condition code bit when an unordered compare is attempted. All arithmetic instructions
also set the FPCC NAN bit if the result of an operation is a NAN. The conditional instructions
interpret the NAN condition code bit equal to one as the unordered condition.
The IEEE 754 standard defines four conditions: equal to (EQ), greater than (GT), less than
(LT), and unordered (UN). In addition, the standard only requires the generation of the con-
dition codes as a result of a floating-point compare operation. The FPU tests for these con-
ditions and 28 others at the end of any operation affecting the condition codes. For purposes
of the floating-point conditional branch, set byte on condition, decrement and branch on con-
dition, and trap on condition instructions, the MC68060 logically combines the four FPCC
bits to form 32 conditional tests. The 32 conditional tests are separated into two groups—16
Table 6-8. Floating-Point Condition Code Encoding
Data Type N Z I NAN
+ Normalized or Denormalized 0000
– Normalized or Denormalized 1000
+ 0 0100
– 0 1100
+ Infinity 0010
– Infinity 1010
+ NAN 0001
– NAN 1001
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