Floating-Point Unit
mode. Thus, the term one-half unit in the last place correctly identifies the error bound for
this operation. This error specification is the relative error present in the result; the absolute
error bound is equal to 2exponent x 2–64. The following example illustrates the error bound
for the other rounding modes:
The difference between the infinitely precise result and the rounded result is 2–64 + 2–65 +
2–66, which is slightly less than 2–63 (the value of the least significant bit). Thus, the error
bound for this operation is not more than one unit in the last place. For all arithmetic opera-
tions, the FPU meets these error bounds, providing accurate and repeatable results.
Most operations end with a postprocessing step. The FPU provides two steps in postpro-
cessing. First, the condition code bits in the FPSR are set or cleared at the end of each arith-
metic operation or move operation to a single floating-point data register. The condition code
bits are consistently set based on the result of the operation. Second, the FPU supports 32
conditional tests that allow floating-point conditional instructions to test floating-point condi-
tions in exactly the same way as the integer conditional instructions test the integer condition
codes. The combination of consistently set condition code bits and the simple programming
of conditional instructions gives the MC68060 a very flexible, high-performance method of
altering program flow based on floating-point results. While reading the summary for each
instruction, it should be assumed that an instruction performs postprocessing unless the
summary specifically states that the instruction does not do so. The following paragraphs
describe postprocessing in detail.
6.4.1 Underflow, Round, and Overflow
During the calculation of an arithmetic result, the FPU arithmetic logic unit (ALU) has more
precision and range than the 80-bit extended-precision format. However, the final result of
these operations is an extended-precision floating-point value. In some cases, an interme-
diate result becomes either smaller or larger than can be represented in extended precision.
Also, the operation can generate a larger exponent or more bits of precision than can be rep-
resented in the chosen rounding precision. For these reasons, every arithmetic instruction
ends by rounding the result and checking for overflow and underflow.
At the completion of an arithmetic operation, the intermediate result is checked to see if it is
too small to be represented as a normalized number in the selected precision. If so, the
UNFL bit is set in the FPSR EXC byte. The MC68060 then takes a nonmaskable underflow
exception and executes the M68060SP underflow exception handler, denormalizing the
result. Denormalizing a number causes a loss of accuracy, but a zero is not returned unless
a gross underflow occurs. If a number has grossly underflowed, the MC68060 takes a non-
maskable underflow exception, and the M68060SP returns a zero or the smallest denormal-
ized number with the correct sign, depending on the rounding mode in effect.
Result Integer 63-Bit Fraction Guard Round Sticky
Intermediate x xxx…x00 1 1 1
Rounded-to-Zero x xxx…x00 0 0 0
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