Floating-Point Unit
Depending on the selected rounding mode or destination data format in effect, the location
of the least significant bit of the mantissa and the locations of the guard, round, and sticky
bits in the 67-bit intermediate result mantissa varies. The guard and round bits are always
calculated exactly. The sticky bit is used to create the illusion of an infinitely wide intermedi-
ate result. As the arrow illustrates in Figure 6-8, the sticky bit is the logical OR of all the bits
in the infinitely precise result to the right of the round bit. During the calculation stage of an
arithmetic operation, any nonzero bits generated that are to the right of the round bit set the
sticky bit to one. Because of the sticky bit, the rounded intermediate result for all required
IEEE arithmetic operations in the RN mode is in error by no more than one-half unit in the
last place.
6.3.2 Rounding the Result
Range control is the process of rounding the mantissa of the intermediate result to the spec-
ified precision and checking the 16-bit intermediate exponent to ensure that it is within the
representable range of the selected rounding-precision format. Range control ensures cor-
rect emulation of a device that only supports single- or double-precision arithmetic. If the
intermediate result’s exponent exceeds the range of the selected precision, the exponent
value appropriate for an underflow or overflow is stored as the result in the 16-bit extended-
precision format exponent. For example, if the data format and rounding mode is single-pre-
cision RM and the result of an arithmetic operation overflows the magnitude of the single-
precision format, the largest normalized single-precision value is stored as an extended-pre-
cision number in the destination floating-point data register (i.e., an unbiased 15-bit expo-
nent of $00FF and a mantissa of $FFFFFF0000000000). If an infinity is the appropriate
result for an underflow or overflow, the infinity value for the destination data format is stored
as the result (i.e., an exponent with the maximum value and a mantissa of zero).
Figure 6-9 illustrates the algorithm that is used to round an intermediate result to the
selected rounding precision and destination data format. If the destination is a floating-point
data register, either the selected rounding precision specified by the FPCR PREC bits or by
the instruction itself determines the rounding boundary. For example, FSADD and FDADD
specify single- and double-precision rounding regardless of the precision specified in the
FPCR PREC bits. If the destination is external memory or an integer data register, the des-
tination data format determines the rounding boundary. If the rounded result of an operation
is not exact, then the INEX2 bit is set in the FPSR EXC byte.
The three additional bits beyond the extended-precision format allow the FPU to perform all
calculations as though it were performing calculations using a float engine with infinite bit
precision. The result is always correct for the specified destination’s data format before per-
forming rounding (unless an overflow or underflow error occurs). The specified rounding
operation then produces a number that is as close as possible to the infinitely precise inter-
mediate value and still representable in the selected precision. The following tie-case exam-
ple illustrates how the 67-bit mantissa allows the FPU to meet the error bound of the IEEE
The least significant bit of the rounded result does not increment even though the guard bit
is set in the intermediate result. The IEEE 754 standard specifies that tie cases should be
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