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Floating-Point Unit
6-2
M68060 USER’S MANUAL
MOTOROLA
The MC68060 FPU has been optimized for the most frequently used instructions and data
types. The MC68060 fully conforms to the
ANSI/IEEE 754–1985 Standard for Binary Float-
ing-Point Arithmetic
. In addition, the MC68060 processor maintains compatibility with the
Motorola extended-precision architecture and is user object code compatible with the
MC68881/MC68882 floating-point coprocessors and the MC68040 microprocessor FPU.
With the inclusion of the M68060SP, the MC68060 provides MC68881/MC68882-compati-
ble software functions. Details on the M68060SP are provided in
Appendix C MC68060
Software Package
.
6.1 FLOATING-POINT USER PROGRAMMING MODEL
Figure 6-2 illustrates the floating-point portion of the user programming model. The following
paragraphs describe the FPU portion of the user programming model for the MC68060. The
model, which is identical to the programming model for the MC68881/MC68882 floating-
point coprocessors, consists of the following registers:
Eight 80-Bit Floating-Point Data Registers (FP7–FP0)
16-Bit Floating-Point Control Register (FPCR)
32-Bit Floating-Point Status Register (FPSR)
32-Bit Floating-Point Instruction Address Register (FPIAR)
Figure 6-1. Floating-Point Unit Block Diagram
EXECUTION UNIT
INSTRUCTION
ATC
INSTRUCTION
CACHE
CONTROLLER
DATA
ATC
DATA
CACHE
CONTROLLER
OPERAND DATA BUS
INSTRUCTION
CACHE
DATA
CACHE
FLOATING-
POINT
UNIT
B
U
S
C
O
N
T
R
O
L
L
E
R
ADDRESS
DATA
INTEGER UNIT
DECODE
DATA AVAILABLE
EA
FETCH
INT
EXECUTE
INSTRUCTION FETCH UNIT
BRANCH
CACHE INSTRUCTION
FETCH
EARLY
DECODE
INSTRUCTION
BUFFER
EA
CALCULATE
DECODE
EA
FETCH
INT
EXECUTE
EA
FETCH
WRITE-BACK
CONTROL
IA
CALCULATE
EA
CALCULATE
INSTRUCTION MEMORY UNIT
DATA MEMORY UNIT
pOEP sOEP
OC OC OC
EX EX
AGAG
DS DS
DA
WB
IB
IED
IC
IAG
FP
EXECUTE
EX
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