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Caches
5-18
M68060 USER’S MANUAL
MOTOROLA
Read misses and write misses to copyback pages cause the cache controller to read a new
cache line from memory into the cache. If available, an invalid line in the selected set is
updated with the tag and data from memory. The line state then changes from invalid to valid
by setting the V-bit for the line. If all lines in the set are already valid or dirty, the pseudo
round-robin replacement algorithm is used to select one of the four lines and replace the tag
and data contents of the line with the new line information. Before replacement, dirty lines
are temporarily buffered and later copied back to memory after the new line has been read
from memory. Snoops always check both the push buffer and the cache. Figure 5-7 illus-
trates the three possible states for a data cache line, with the possible transitions caused by
either the processor or snooped accesses. Transitions are labeled with a capital letter, indi-
cating the previous state, followed by a number indicating the specific case listed in Table
5-3.
Figure 5-7. Data Cache Line State Diagrams
WI1— CPU READ MISS
WI6—CPUSH WV4—CPU WRITE HIT
WV5— CINV
WV7—SNOOP HIT
WV6— CPUSH
WI5—CINV
WI3—CPU WRITE MISS WV3—CPU WRITE MISS
WV2—CPU READ HIT
WV1—CPU READ MISS
COPYBACK
CI6— CPUSH
CI5— CINV
CV2—CPU READ HIT
CV1—CPU READ MISS
CD3—CPU WRITE MISS
CD2— CPU READ HIT
CD4—CPU WRITE HIT
CV5—CINV
CV7—SNOOP HIT
CV6—CPUSH
CI1—CPU READ MISS
CD1—CPU
CD5—CINV
CD7—SNOOP HIT
CD6—CPUSH CV3—CPU WRITE MISS
CV4—CPU WRITE HIT
CI3— CPU
COPYBACK CACHING MODE
WRITETHROUGH CACHING MODE
INVALID COPYBACK
VALID
COPYBACK
DIRTY
WRITE-
THROUGH
INVALID VALID
WRITE-
THROUGH
WRITE MISS
READ MISS
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