M68060 USER’S MANUAL
5.12.2 Data Cache
The integer unit uses the data cache to store operand data as it requires or generates the
data. The data cache supports a line-based protocol allowing individual cache lines to be in
one of three states: invalid, valid, or dirty. To maintain coherency with memory, the data
cache supports both writethrough and copyback modes, specified by the CM field for the
Table 5-2. Instruction Cache Line State Transitions
Cache Operation Current State
Invalid Cases Valid Cases
IPU Read Miss I1 Read line from memory; supply data to
IPU and update cache; go to valid state. V1 Read line from memory; supply data to
IPU and update cache (replacing old
line); remain in current state.
IPU Read Hit I2 Not Possible. V2 Suppply data to IPU; remain in current
Cache Invalidate or Push
(CINV or CPUSH) I3 No action; remain in current state. V3 No action; go to invalid state.
Alternate Master Snoop Hit
(Read or Write) I4 Not possible. V4 No action; go to invalid state.
Alternate Master Snoop Miss I5 Not possible. V5 No action; remain in current state.
TCI Asserted on Read Miss
(during the First Access) I6 Read line for memory; Supply data to
the IPU; remain in current state. V6 Not Possible.
Figure 5-6. Instruction Cache Line State Diagram
I1—IPU READ MISS
V1—IPU READ MISS
V2—IPU READ HIT
V4—SNOOP READ/WRITE HIT