vide a mechanism that allows the instruction fetch pipeline to detect and change instruction
streams before the change-of-flow instructions enter an operand execution pipeline.
The branch cache implementation is made up of a five-state prediction model based on past
execution history, in addition to the current program counter/branch target virtual address
association logic.
For each instruction fetch address generated, the branch cache is examined to see if a valid
branch entry is present. If there is not a branch cache hit, the instruction fetch unit continues
to fetch instructions sequentially. If a branch cache hit occurs indicating a “taken branch”,
the instruction fetch unit discards the current instruction steam and begins fetching at the
location indicated by the branch target address. As long as the branch cache prediction is
correct, which happens a very significant percentage of the time, the change-of-flow of the
instruction stream is “invisible” to the OEP and performance is maximized. If the branch
cache prediction is wrong, the internal pipelines are “cancelled” and the correct instruction
flow is established.
The branch cache must be cleared by the operating system on all context switches (using
the MOVEC to CACR instruction), because it is virtually-mapped.
The branch cache is automatically cleared by the hardware as part of any cache invalidate
(CINV) or any cache push and invalidate (CPUSH) instruction operating on the instruction
Programs that use the TRAPF instruction extension word as a possible branch target desti-
nation intefere with proper operation of the branch target cache, resulting in an access error
exception. This condition is indicated by the BPE bit in the FSLW of the access error stack.
The instruction and data caches function independently when servicing access requests
from the integer unit. The following paragraphs discuss the operational details for the caches
and present state diagrams depicting the cache line state transitions.
5.12.1 Instruction Cache
The integer unit uses the instruction cache to store instruction prefetches as it requests
them. Instruction prefetches are normally requested from sequential memory locations
except when a change of program flow occurs (e.g., a branch taken) or when an instruction
that can modify the status register (SR) is executed, in which case the instruction pipe is
automatically flushed and refilled. The instruction cache supports a line-based protocol that
allows individual cache lines to be in either the invalid or valid states.
For instruction prefetch requests that hit in the cache, the long word containing the instruc-
tion is places onto the internal instruction data bus. When an access misses in the cache,
the cache controller requests the line containing the required data from memory and places
it in the cache. If available, an invalid line is selected and updated with the tag and data from
memory. The line state then changes from invalid to valid by setting the V-bit. If all lines in
the set are already valid, a pseudo round-robin replacement algorithm is used to select one
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