required. In the case of an instruction cache line fill, the unneeded data from the aborted
cycle is completely ignored.
The MC68060 supports native retry functionality using the TRA signal, as well as MC68040-
compatible retry functionality using TA and TEA. The MC68040-compatible retry functions
as the 040. For either type, on the initial access of a line read, a retry termination causes a
retry of the bus cycle. A MC68040-compatible retry signaled during the remaining cycles of
the line access (either burst or pseudo-burst) is recognized as a bus error, and the proces-
sor handles it as described in the previous paragraphs. Assertion of the TRA signal (native
retry) during the remaining cycles of the line access is ignored.
5.7.2 Cache Pushes
When the cache controller selects a dirty data cache line for replacement, memory must be
updated with the dirty data before the line is replaced. Cache pushes occur for line replace-
ment, as required for the execution of the CPUSH instruction, and when a writethrough or
cache-inhibited access hits a dirty cache line. To reduce the requested data’s latency in the
new line, the dirty line being replaced is temporarily placed in a push buffer while the new
line is fetched from memory. When a line is allocated to the push buffer, an alternate bus
master can snoop it, but the execution units cannot access it. After the bus transfer for the
new line successfully completes, the dirty cache line is copied back to memory, and the push
buffer is invalidated. If the operation to access the replacement line is abnormally terminated
or the external cache inhibit signal is asserted, the line in the push buffer is restored back
into its original position in the cache and validated.
A cache line is written to memory using a line push transfer if it is dirty. A push transfer is
distinguished from a normal write transfer by an encoding of 000 on the transfer modifier sig-
nals (TM2–TM0) for the push. Refer to
Section 8 Exception Processing
for information on
the case of a bus error terminating a push transfer.
A dirty cache line hit by a cache-inhibited access is pushed before the external bus access
The MC68060 processor implements a push buffer to reduce latency for requested new data
on a cache miss by temporarily putting displaced dirty data into the push buffer while the
new data is fetched from memory. While the dirty line resides in the push buffer, it can be
snooped by an external bus master. The push buffer contains 16 bytes of storage (one dis-
placed cache line).
If a data cache miss displaces a dirty line, the miss reference is immediately placed on the
system bus. While waiting for the response, the current contents of the data cache location
are loaded into the push buffer. Once the bus transaction (burst read) completes, the
MC68060 is able to generate the appropriate line write bus transaction to store the contents
of the push buffer into memory.
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