four cycles. The bursting mechanism requires addresses to wrap around so that the entire
four long words in the cache line are filled in a single operation.
When a cache line read is initiated, the first cycle attempts to load the line entry correspond-
ing to the address requested by the IFU. Subsequent transfers are for the remaining entries
in the cache line. In the case of a misaligned access in which the operand spans two line
entries, the first cycle corresponds to the line entry containing the portion of the operand at
the lower address.
Line read data is handled differently by the instruction cache and the data cache. In the
instruction cache, the first long word fetched is immediately available to the IFU. It is also
put in a line read buffer. The data for the rest of the line is also put in this buffer as it is
received. If subsequent IFU requests are sequential and within the address range in the line
read buffer, these requests hit in the instruction read buffer as data becomes available. If
subsequent IFU requests are not sequential, or are outside the address range in the read
buffer, the IFU stalls until the line is completely fetched. In the data cache, the first long word
or first two long words are available to the integer or floating-point units. The amount of data
which is available immediately depends on the size and alignment of the operation that ini-
tiated the cache miss. These long words along with the remainder of the line fetch are also
put in the data line read buffer. All subsequent data cache requests stall until the line is com-
pletely fetched. A misaligned access which spans two cache lines is handled by the data
cache unit as two separate accesses.
The assertion of TCI during the first cycle of a burst read operation inhibits loading of the
buffered line into the cache, but it does not cause the burst transfer (or pseudo-burst transfer
if TBI is asserted with TCI) to be terminated early. If TCI is asserted during the first data
transfer cycle for a read operand, the initial bypass of data for both instruction and data
accesses takes place normally, as described above in the paragraph on line reads. The line
read buffers in both caches are filled normally. The instruction cache unit will allow sequen-
tial access in the address range of the line read buffer until the last long word of the burst is
transferred from the bus controller. No additional data from the line is available from the data
cache unit. When the line fetch is completed, the contents of both line buffers are discarded.
No data is transferred to either cache memory. The assertion of TCI is ignored during the
second, third, or fourth cycle of a burst operation and is ignored for write operations.
A bus error occurring during a burst operation causes the burst operation to abort. If the bus
error occurs during the first cycle of a burst, the data from the bus is ignored. If the access
is a data cycle, exception processing proceeds immediately. If the cycle is for an instruction
prefetch, a bus error exception is not taken immediately, but will be taken if the instruction
flow subsequently causes the instruction to be attempted. Refer to
Section 7 Bus Opera-
for more information about pipeline operation.
For either cache, when a bus error occurs on the second cycle or later, the burst operation
is aborted and the line buffer is invalidated. The processor may or may not take an excep-
tion, depending on the status of the pending data request. If the bus error cycle contains a
portion of a data operand that the processor is specifically waiting for (e.g., the second half
of a misaligned operand), the processor immediately takes an exception. Otherwise, no
exception occurs, and the cache line fill is repeated the next time data within the line is
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