Accesses to pages specified as writethrough are always
written to the external address, although the cycle can be buffered (depending on the state
of the ESB bit in the CACR). Writes in writethrough mode are handled with a no-write-allo-
cate policy—i.e., writes that miss in the data cache are written to memory or the write buffer,
but do not cause the corresponding line in memory to be loaded into the cache. Write
accesses that hit always write through to memory and update matching cache lines. Spec-
ifying writethrough mode for the shared pages maintains cache coherency for shared mem-
ory areas in a multiprocessing environment. The cache supplies data to instruction or data
read accesses that hit in the appropriate cache; misses cause a new cache line to be loaded
into the cache, unless no-allocate mode is selected (NAD or NAI is set) via the CACR. COPYBACK MODE.
Copyback pages are typically used for local data structures or
stacks to minimize external bus usage and reduce write access latency. Write accesses to
pages specified as copyback that hit in the data cache update the cache line and set the
corresponding D-bit without an external bus access. The dirty cached data is only written to
memory if the line is replaced due to a miss, or a writethrough or cache-inhibited access
which hits the dirty line, or a CPUSH which pushes the line. If a write access misses in the
cache, then the needed cache line is read from memory and the cache is updated if the NAD
bit in the CACR is clear. If a write miss occurs when the NAD bit is set, the cache is not
updated. When a miss causes a dirty cache line to be selected for replacement, the current
cache line data is moved to the push buffer. The replacement line is read into the cache, and
the push buffer contents are written to external memory.
5.4.2 Cache-Inhibited Accesses
Address space regions containing targets such as I/O devices and shared data structures
in multiprocessing systems can be designated cache inhibited. If a page descriptor’s CM
field indicates precise or imprecise, then the access is cache inhibited. The caching opera-
tion is identical for both cache-inhibited modes. The difference between these inhibited
cache modes has to do with recovery from an exception (either external bus error, or inter-
If the CM field of a matching address indicates either precise or imprecise modes, the cache
controller bypasses the cache and performs an external bus transfer. The data associated
with the access is not cached internally, and the cache inhibited out (CIOUT) signal is
asserted during the bus cycle to indicate to external memory that the access should not be
cached. If the data cache line is already resident in an internal cache and the current cache
mode for that page becomes cache inhibited, either through an operating system change,
or due to a shared physical page, then the caches provide additional support for cache
coherency, by pushing the line if dirty or invalidating the line if it is valid.
If the CM field indicates precise mode, then the sequence of read and write accesses to the
page is guaranteed to match the sequence of the instruction order. In imprecise mode, the
operand pipeline allows read accesses that hit in the cache to occur before completion of a
pending write from a previous instruction. Writes will not be deferred past operand read
accesses that miss in the cache (i.e. that must be read from the bus). Precise operation
forces operand read accesses for an instruction to occur only once by preventing the instruc-
tion from being interrupted after the operand fetch stage. Otherwise, if not in precise mode
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