field. The four tags from the selected cache set are compared with the tag reference. If any
one of the four tags matches the tag reference and the tag status is either valid or dirty, then
a cache hit has occurred. A cache hit indicates that the data entries (LW3–LW0) in that
cache line contain valid data (for a read access) or is written with new data (for a write ac-
To allocate an entry into the cache, the physical address bits 10–4 are used to index into the
cache and select one of the 128 sets of cache lines. The status of each of the four cache
lines is examined. The cache control logic first looks for an invalid cache line to use for the
new entry. If no invalid cache lines are available, then one of the four cache lines must be
deallocated to host the new entry. The cache controller uses a pseudo round-robin replace-
ment algorithm to determine which cache line will be deallocated and replaced.
In the process of deallocation, a cache line that is valid and not dirty is invalidated. A dirty
cache line is placed in a push buffer (to do an external cache line write push) before being
invalidated. Once a cache line is invalidated, it is replaced with the new entry.
When a cache line is selected to host a new cache entry, the new physical address bits 31–
11 are written to the tag, the data bits LW3–LW0 are updated with the new memory data,
and the cache line status is changed to a valid state. Allocating a new entry into the cache
is always associated with a visible cache line read bus cycle externally.
Read cycles that miss in the cache allocate normally as described in the previous para-
graphs. Write cycles that miss in the cache do not allocate on a cachable writethrough page,
but do allocate on a cachable copyback page. The allocation process initiates a line read to
allocate a valid entry in the cache as previously described, and is immediately followed by
a write to the newly allocated cache line changing the cache line status to dirty. No external
write to memory occurs.
Read hits do not change the cache status of the cache line that hit and no deallocation and
replacement occurs. Write hits on cachable writethrough pages perform an external write
bus cycle; write hits on cachable copyback pages do not perform an external bus cycle.
If the instruction cache hits on an instruction fetch access, one long word is driven onto the
internal instruction data bus. If the operand data cache hits on an operand read access, 32-
bits or 64-bits (for double-precision floating-point accesses) are driven onto the internal op-
erand data bus. If the data cache hits on a write access, the data is written to the appropriate
portion of the accessed cache line. If the data access is misaligned, then the operand cache
controller breaks up the access into a sequence of smaller aligned fetches to the data cache.
Any misaligned operand reference generates at least two cache accesses. Since the entry
validity is provided only on a line basis, the entire line must be loaded from system memory
on a cache miss in order for a cache to be able to contain any valid information for that line
Non-cachable addresses (i.e., those designated as cache inhibited by the memory manage-
ment unit (MMU) page descriptor or transparent translation register) bypass the cache to al-
low support for I/O, etc. Valid data cache entries that match during non-cachable address
accesses are pushed and invalidated if dirty and are invalidated if not dirty.
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