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Caches
MOTOROLA
M68060 USER’S MANUAL
5-3
have the V-bit and D-bit set, indicating that the line has valid entries that have not been writ-
ten to memory. A cache line changes states from valid or dirty to invalid if the execution of
the CINV or CPUSH instruction explicitly invalidates the cache line or if a snooped access
hits the cache line. Both caches should be explicitly cleared using the CINVA instruction
after a hardware reset of the processor since reset does not invalidate the cache lines.
Figure 5-4 illustrates the general flow of a caching operation. The caches use the physical
addresses, and to simplify the discussion, the discussion of the translation of logical to phys-
ical addresses is omitted.
To determine if the physical address is already allocated in the cache, the lower physical
address bits 10–4 are used to index into the cache and select 1 of 128 sets of cache lines.
Physical address bits 31–11 are used as a tag reference or to update the cache line tag
Figure 5-4. Caching Operation
TAG DATA/TAG REFERENCE INDEX
31 10
0
COMPARATOR
1
3
2
HIT 3
HIT 2
HIT 1
HIT 0
HIT
TAG STATUS
TAG STATUS
SET 0
SET 1
SET 128
LINE 0
LINE 1
LINE 2
LINE 3
LW0 LW1 LW2 LW3
LW0 LW1 LW2 LW3
MUX
LOGICAL OR
LINE SELECT
DATA OR
INSTRUCTION
PHYSICAL
SET SELECT
PA10–PA4
PHYSICAL ADDRESS
TRANSLATED
PHYSICAL
ADDRESS
PA31–PA11
4
11 30
PA31-PA11
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