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Caches
5-2
M68060 USER’S MANUAL
MOTOROLA
bit for the line. Note that only the data cache supports dirty cache lines. Figure 5-2 illustrates
the instruction cache line format and Figure 5-3 illustrates the data cache line format.
The cache stores an entire line, providing validity on a line-by-line basis. Only burst mode
accesses that successfully read four long words can be cached.
A cache line is always in one of three states: invalid, valid, or dirty. For invalid lines, the V-
bit is clear, causing the cache line to be ignored during lookups. Valid lines have their V-bit
set and D-bit cleared, the line contains valid data consistent with memory. Dirty cache lines
Figure 5-1. MC68060 Instruction and Data Caches
TAG V LW3 LW2 LW1 LW0
WHERE:
TAG—21-BIT PHYSICAL ADDRESS TAG
V—VALID BIT FOR LINE
LWn—LONG WORD n (32-BIT) DATA ENTRY
Figure 5-2. Instruction Cache Line Format
TAG V D LW3 LW2 LW1 LW0
WHERE:
TAG—21-BIT PHYSICAL ADDRESS TAG
V—VALID BIT FOR LINE
D—DIRTY BIT FOR LINE
LWn—LONG WORD n (32-BIT) DATA ENTRY
Figure 5-3. Data Cache Line Format
EXECUTION UNIT
INSTRUCTION
ATC
INSTRUCTION
CACHE
CONTROLLER
DATA
ATC
DATA
CACHE
CONTROLLER
OPERAND DATA BUS
INSTRUCTION
CACHE
DATA
CACHE
FLOATING-
POINT
UNIT
B
U
S
C
O
N
T
R
O
L
L
E
R
ADDRESS
DATA
INTEGER UNIT
DECODE
DATA AVAILABLE
EA
FETCH
INT
EXECUTE
INSTRUCTION FETCH UNIT
BRANCH
CACHE INSTRUCTION
FETCH
EARLY
DECODE
INSTRUCTION
BUFFER
EA
CALCULATE
DECODE
EA
FETCH
INT
EXECUTE
EA
FETCH
WRITE-BACK
CONTROL
IA
CALCULATE
EA
CALCULATE
INSTRUCTION MEMORY UNIT
DATA MEMORY UNIT
pOEP sOEP
OC OC OC
EX EX
AGAG
DS DS
DA
WB
IB
IED
IC
IAG
FP
EXECUTE
EX
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