The MC68060 contains two independent 8-Kbyte, on-chip caches which can be accessed
simultaneously for instruction and operand data. The caches improve system performance
by providing low latency data to the MC68060 instruction and data pipes. This decouples
processor performance from system memory performance and increases bus availability for
alternate bus masters.
As shown in Figure 5-1, the instruction and data caches are contained in the instruction and
data memory units. The appropriate memory unit independently services instruction
prefetch from the instruction fetch unit (IFU) and data requests from the operand pipe unit
(OPU). The memory units translate the logical address in parallel with indexing into the
cache. If the translated (physical) address matches one of the cache entries, the access hits
in the cache. For a read operation, the memory unit supplies the data to the IPU instruction
buffer or the OPU, and for a write operation, the memory unit updates the cache. If the
access does not match one of the cache entries (misses in the cache) or a write access must
be written through to memory, the appropriate memory unit sends an external bus request
to the bus controller. The bus controller then reads or writes the required data. In the event
that the bus controller receives an external bus request from both memory units, the bus
controller invokes its priority scheme to choose between IPU and OPU requests.
To maintain cache coherency, the MC68060 provides automatic snoop-invalidation when it
is not the bus master. Unlike the MC68040, the MC68060 cannot not source or sink cache
data during alternate bus master accesses.
The MC68060 implements a bus snooper that maintains cache coherency by monitoring an
alternate bus master access to memory and invalidating matching cache lines during the
alternate bus master access. The MC68060 requires that memory pages shared with other
bus masters be cache inhibited or marked cachable writethrough (instead of copyback).
When a processor writes to writethrough pages, external memory is always updated through
an external bus access after updating the cache, keeping memory and cached data consis-
Both four-way set-associative caches have 128 sets of four 16-byte lines. Each set in both
caches has a tag (consisting of the upper 21 bits of the physical address), status information,
and four long words (128 bits) of data. The status information for the instruction cache is a
single valid bit for the line. The status information for the data cache is a valid bit and a dirty
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