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Table of Contents
xii
M68060 USER’S MANUAL
MOTOROLA
4.6.2 Effect of MDIS on Address Translation .................................................... 4-30
4.7 MMU Instructions........................................................................................ 4-30
4.7.1 MOVEC .................................................................................................... 4-30
4.7.2 PFLUSH ................................................................................................... 4-30
4.7.3 PLPA ........................................................................................................ 4-30
Section 5
Caches
5.1 Cache Operation........................................................................................... 5-1
5.2 Cache Control Register ................................................................................ 5-5
5.3 Cache Management ..................................................................................... 5-6
5.4 Caching Modes............................................................................................. 5-7
5.4.1 Cachable Accesses .................................................................................... 5-7
5.4.1.1 Writethrough Mode................................................................................... 5-7
5.4.1.2 Copyback Mode ....................................................................................... 5-8
5.4.2 Cache-Inhibited Accesses .......................................................................... 5-8
5.4.3 Special Accesses ....................................................................................... 5-9
5.5 Cache Protocol ............................................................................................. 5-9
5.5.1 Read Miss................................................................................................... 5-9
5.5.2 Write Miss................................................................................................... 5-9
5.5.3 Read Hit...................................................................................................... 5-9
5.5.4 Write Hit.................................................................................................... 5-10
5.6 Cache Coherency ....................................................................................... 5-10
5.7 Memory Accesses for Cache Maintenance ................................................ 5-11
5.7.1 Cache Filling............................................................................................. 5-11
5.7.2 Cache Pushes .......................................................................................... 5-13
5.8 Push Buffer ................................................................................................. 5-13
5.9 Store Buffer................................................................................................. 5-13
5.10 Push Buffer and Store Buffer Bus Operation.............................................. 5-14
5.11 Branch Cache ............................................................................................. 5-14
5.12 Cache Operation Summary ........................................................................ 5-15
5.12.1 Instruction Cache...................................................................................... 5-15
5.12.2 Data Cache............................................................................................... 5-16
Section 6
Floating-Point Unit
6.1 Floating-Point User Programming Model...................................................... 6-2
6.1.1 Floating-Point Data Registers (FP7–FP0) .................................................. 6-3
6.1.2 Floating-Point Control Register (FPCR) ..................................................... 6-3
6.1.2.1 Exception Enable Byte ............................................................................. 6-3
6.1.2.2 Mode Control Byte.................................................................................... 6-3
6.1.3 Floating-Point Status Register (FPSR)....................................................... 6-4
6.1.3.1 Floating-Point Condition Code Byte ......................................................... 6-5
6.1.3.2 Quotient Byte............................................................................................ 6-5
6.1.3.3 Exception Status Byte .............................................................................. 6-5
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