access in which the operand spans two line entries, the first cycle corresponds to the line
entry containing the portion of the operand at the lower address.
The cache controller temporarily stores the data from each cycle in a line read buffer,
where it is immediately available to the IU. If a misaligned access spans two entries in the
line, the second portion of the operand is available to the IU as soon as the second
memory cycle completes. A new IU access that hits the cache line being filled is also
supplied data as soon as the required long word has been received from the bus
controller. During the period required to fill the buffer, other IU accesses that hit in the
cache are supplied data. This is vertical for a short cache-inhibited code loop that is less
than eight bytes in length. Subsequent interactions of the loop hit in the buffer, but appear
to hit in the cache since there is no external bus activity associated with the reads.
The assertion of TCI during the first cycle of a burst read operation inhibits loading of the
buffered line into the cache, but it does not cause the burst transfer (or pseudo-burst
transfer if TBI is asserted with TCI) to be terminated early. The data placed in the buffer is
accessible by the IU until the last long word of the burst is transferred from the bus
controller, after which the contents of the buffer are invalidated without being copied into
the cache. The assertion of TCI is ignored during the second, third, or fourth cycle of a
burst operation and is ignored for write operations.
A bus error occurring during a burst operation causes the burst operation to abort. If the
bus error occurs during the first cycle of a burst, the data from the bus is ignored. If the
access is a data cycle, exception processing proceeds immediately. If the cycle is for an
instruction prefetch, a bus error exception is pending. The bus error is processed only if
the IU attempts to use either instruction word. Refer to Section 7 Bus Operation for more
information about pipeline operation.
For either cache, when a bus error occurs on the second cycle or later, the burst operation
is aborted and the line buffer is invalidated. The processor may or may not take an
exception, depending on the status of the pending data request. If the bus error cycle
contains a portion of a data operand that the processor is specifically waiting for (e.g., the
second half of a misaligned operand), the processor immediately takes an exception.
Otherwise, no exception occurs, and the cache line fill is repeated the next time data
within the line is required. In the case of an instruction cache line fill, the data from the
aborted cycle is completely ignored.
On the initial access of a line read, a retry (indicated by the assertion of TA and TEA)
causes the bus controller to retry the bus cycle. However, a retry signaled during the
remaining cycles of the line access (either burst or pseudo-burst) is recognized as a bus
error, and the processor handles it as described in the previous paragraphs.
A cache inhibit or bus error on a line read can change the state of the line being replaced,
even though the new line is not copied into the cache. Before loading a new line, the
cache line being replaced is copied to the push buffer; if it is dirty, the cache line is
invalidated. If a cache inhibit or bus error occurs on a replacement line read, a dirty line is
restored to the cache from the push buffer. However, the line being replaced is not
restored in the cache if it was originally valid and the cache line remains invalid. If the line
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