avoided by pushing cache lines when a page descriptor is changed and ensuring that
alternate bus masters indicate the appropriate snoop operation for writes to corresponding
pages (i.e., mark invalid for write-through pages and sink data for copyback pages). If the
access is copyback, the cache controller updates the cache line and sets the D-bit for of
the appropriate long words in the cache line. An external write is not performed, and the
cache line state changes to, or remains in, the dirty state.
An alternate bus master can drive the SCx signals for a write access with an encoding that
indicates to the M68040 that it should sink the data, inhibit memory, and respond as a
slave if the access hits in the cache. The cache operation depends on the access size and
current line state. A snooped line write that hits a valid line always causes the
corresponding cache line to be invalidated. For snooped writes of byte, word, or long-word
size that hit a dirty line, the processor inhibits memory and responds to the alternate bus
master as a slave, sinking the data. Data received from the alternate bus master is written
to the appropriate long word in the cache line, and the D-bit is set for that entry. The cache
controller invalidates a cache line if the snoop control pins have indicated that a matching
cache line is marked invalid for a snoop write.
The M68040 provides several different mechanisms to assist in maintaining cache
coherency in multimaster systems. Both write-through and copyback memory update
techniques are supported to maintain coherency between the data cache and memory.
Alternate bus master accesses can reference data that the M68040 caches, causing
coherency problems if the accesses are not handled properly. The M68040 snoops the
bus during alternate bus master transfers. If a write access hits in the cache, the M68040
can update its internal caches, or if a read access hits, it can intervene in the access to
supply dirty data. Caches can be snooped even if they are disabled. The alternate bus
master controls snooping through the snoop control signals, indicating which access can
be snooped and the required operation for snoop hits. Table 4-1 lists the requested snoop
operation for each encoding of the snoop control signals. Since the processor and the bus
snooper must both access the caches, the snoop controller has priority over the processor
for snoopable accesses to maintain cache coherency.
Table 4-1. Snoop Control Encoding
Requested Snoop Operation
SC1 SC0 Alternate Bus Master Read Access Alternate Bus Master Write Access
0 0 Inhibit Snooping Inhibit Snooping
0 1 Supply Dirty Data and Leave Dirty Data Sink Byte/Word/Long/Long Word
1 0 Supply Dirty Data and Mark Line Invalid Invalidate Line
1 1 Reserved (Snoop Inhibited) Reserved (Snoop Inhibited)
The snooping protocol and caching mechanism supported by the M68040 are optimized to
support multimaster systems with the M68040 as the single caching master. In systems
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