Loading...
4- 8 M68040 USER'S MANUAL MOTOROLA
only if the bus transfer is marked as snoopable on the bus. The protocols described in the
following paragraphs assume that the data is cachable (i.e., write-through and copyback).
4.4.1 Read Miss
A processor read that misses in the cache causes the cache controller to request a bus
transaction that reads the needed line from memory and supplies the required data to the
IU. The line is placed in the cache in the valid state. Snooped external reads that miss in
the cache have no affect on the cache.
4.4.2 Write Miss
The cache controller handles processor writes that miss in the cache differently for write-
through and copyback pages. Write misses to copyback pages cause the processor to
perform a bus transaction that writes the needed cache line into its cache from memory in
the same manner as for a read miss. The new cache line is then updated with the write
data, and the D-bits are set for each long word that has been modified, leaving the cache
line in the dirty state. Write misses to write-through pages write directly to memory without
loading the corresponding cache line in the cache. Snooped external writes that miss in
the cache have no affect on the cache.
4.4.3 Read Hit
The cache controller handles processor reads that hit in the cache differently for write-
through and copyback pages. No bus transaction is performed, and the state of the cache
line does not change. Physical address bit 3 selects either the upper or lower half-line
containing the required operand. This half-line is driven onto the internal bus. If the
required data is allocated entirely within the half-line, only one access into the cache is
required. Because the organization of the cache does not allow selection of more than one
half-line at a time, misalignment across a half-line boundary requires two accesses into
the cache.
A snooped external read that hits in the cache is ignored if the cache line is valid. If the
snooped access hits a dirty line, memory is inhibited from responding, and the data is
sourced from the cache directly to the alternate bus master. A snooped read hit does not
change the state of the cache line unless the snooped access also indicates mark invalid,
which causes the line to be invalidated after the access, even if it is dirty. Alternate bus
masters should indicate mark invalid only for line reads to ensure the entire line is
transferred before invalidating.
4.4.4 Write Hit
The cache controller handles processor writes that hit in the cache differently for write-
through and copyback pages. For write-through accesses, a processor write hit causes
the cache controller to update the affected long-word entries in the cache line and to
request an external memory write transfer to update memory. The cache line state does
not change. A write-through access to a line containing dirty data constitutes a system
programming error even if the D-bits for the line are unchanged. This situation can be
Loading...
Terms of Use | Privacy Policy | DMCA Policy
2006-2020 Rsmanuals.com