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MOTOROLA M68040 USER’S MANUAL 4- 7
4.3.2 Cache-Inhibited Accesses
Address space regions containing targets such as I/O devices and shared data structures
in multiprocessing systems can be designated cache inhibited. If a page descriptor’s CM
field indicates nonserialized or serialized, then the access is cache inhibited. The caching
operation is identical for both cache-inhibited modes. If the CM field of a matching address
indicates either nonserialized or serialized modes, the cache controller bypasses the
cache and performs an external bus transfer. The data associated with the access is not
cached internally, and the cache inhibited out (CIOUT) signal is asserted during the bus
transfer to indicate to external memory that the access should not be cached. If the data
cache line is already resident in an internal cache, then the data cache line is pushed from
the cache if it is dirty or the data cache line is invalidated if it is valid.
If the CM field indicates serialized, then the sequence of read and write accesses to the
page is guaranteed to match the sequence of the instruction order. Without serialization,
the IU pipeline allows read accesses to occur before completion of a write-back for a
previous instruction. Serialization forces operand read accesses for an instruction to occur
only once by preventing the instruction from being interrupted after the operand fetch
stage. Otherwise, the instruction is aborted, and the operand is accessed when the
instruction is restarted. These guarantees apply only when the CM field indicates the
serialized mode and the accesses are aligned. Regardless of the selected cache mode,
locked accesses are implicitly serialized. The TAS, CAS, and CAS2 instructions use
locked accesses for operands in memory and for updating translation table entries during
table search operations.
4.3.3 Special Accesses
Several other processor operations result in accesses that have special caching
characteristics besides those with an implied cache-inhibited access in the serialized
mode. Exception stack accesses, exception vector fetches, and table searches that miss
in the cache do not allocate cache lines in the data cache, preventing replacement of a
cache line. Cache hits by these accesses are handled in the normal manner according to
the caching mode specified for the accessed address.
Accesses by the MOVE16 instruction also do not allocate cache lines in the data cache for
either read or write misses. Read hits on either valid or dirty cache lines are read from the
cache. Write hits invalidate a matching line and perform an external access. Interacting
with the cache in this manner prevents a large block move or block initialization
implemented with a MOVE16 from being cached, since the data may not be needed
immediately.
If the data cache is re-enabled after a locked access has hit and the data cache was
disabled, the next non-locked access that results in a data cache miss will not be cached.
4.4 CACHE PROTOCOL
The cache protocol for processor and snooped accesses is described in the following
paragraphs. In all cases, an external bus transfer will cause a cache line state to change
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