entire cache, and can select one or both caches for the operation. For line and page
operations, a physical address in an address register specifies the memory address.
Every IU access to the cache has an associated caching mode that determines how the
cache handles the access. An access can be cachable in either the write-through or
copyback modes, or it can be cache inhibited in nonserialized or serialized modes. The
CM field corresponding to the logical address of the access normally specifies, on a page-
by-page basis, one of these caching modes. The default memory access caching mode is
nonserialized. When the cache is enabled and memory management is disabled, the
default caching mode is write-through. The transparent translation registers and MMUs
allow the defaults to be overridden. In addition, some instructions and IU operations
perform data accesses that have an implicit caching mode associated with them. The
following paragraphs discuss the different caching accesses and their related cache
4.3.1 Cachable Accesses
If a page descriptor’s CM field indicates write-through or copyback, then the access is
cachable. A read access to a write-through or copyback page is read from the cache if
matching data is found. Otherwise, the data is read from memory and used to update the
cache. Since instruction cache accesses are always reads, the selection of write-through
or copyback modes do not affected them. The following paragraphs describe the write-
through and copyback modes in detail. WRITE-THROUGH MODE. Accesses to pages specified as write-through are
always written to the external address, although the cycle can be buffered, keeping
memory and cache data consistent. Writes in write-through mode are handled with a no-
write-allocate policy—i.e., writes that miss in a data cache are written to memory but do
not cause the corresponding line in memory to be loaded into the cache. Write accesses
always write through to memory and update matching cache lines. Specifying write-
through mode for the shared pages maintains cache coherency for shared memory areas
in a multiprocessing environment. The cache supplies data to instruction or data read
accesses that hit in the appropriate cache; misses cause a new cache line to be loaded
into the cache, replacing a valid cache line if there are no invalid lines. COPYBACK MODE. Copyback pages are typically used for local data structures
or stacks to minimize external bus usage and reduce write access latency. Write accesses
to pages specified as copyback that hit in the data cache update the cache line and set
the corresponding D-bits without an external bus access. The dirty cached data is only
written to memory if 1) the line is replaced due to a miss, 2) a cache inhibited access
matches the line, or 3) the CPUSH instruction explicitly pushes the line. If a write access
misses in the cache, the memory unit reads the needed cache line from memory and
updates the cache. When a miss causes a dirty cache line to be selected for replacement,
the memory unit places the line in an internal copyback buffer. The replacement line is
read into the cache, and writing the dirty cache line back to memory updates memory.
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