4- 4 M68040 USER'S MANUAL MOTOROLA
SPAGE FRAME PAGE OFFSET
31 12 0
ADDRESS
TRANSLATION
CACHE
PA11–PA10
0
COMPARATOR
1
3
2
HIT 3
HIT 2
HIT 1
HIT 0
HIT
TAG STATUS
TAG STATUS
SET 0
SET 1
SET 63
LINE 0
LINE 1
LINE 2
LINE 3
D0 D1 D2 D3
D0 D1 D2 D3
MUX
LOGICAL OR
LINE SELECT
DATA OR
INSTRUCTION
PHYSICAL
SET SELECT
PA9–PA4
SUPERVISOR
BIT
LA31–LA12
LOGICAL ADDRESS
PA31–PA12
TRANSLATED
PHYSICAL
ADDRESS
PA31–PA10
Figure 4-3. Caching Operation
Both caches contain circuitry to automatically determine which cache line in a set to use
for a new line. The cache controller locates the first invalid line and uses it; if no invalid
lines exist, then a pseudo-random replacement algorithm is used to select a valid line,
replacing it with the new line. Each cache contains a 2-bit counter, which is incremented
for each access to the cache. The instruction cache counter is incremented for each half-
line accessed in the instruction cache. The data cache counter is incremented for each
half-line accessed during reads, for each full line accessed during writes in copyback
mode, and for each bus transfer resulting from a write in write-through mode. When a
miss occurs and all four lines in the set are valid, the line pointed to by the current counter
value is replaced, after which the counter is incremented.
