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MOTOROLA M68040 USER'S MANUAL 3- 31
instruction, and the stacked FA points to the first longword in the missing page. When an
ATC access error occurs while prefetching the next instruction on the non-existant page
after a change of flow instruction, the exception should be cleared by execution of the new
instruction flow. Either avoid this scenario, or have a dummy resident page following the
exceptional instruction.
Figure 3-22 illustrates a general flowchart for address translation. The top branch of the
flowchart applies to transparent translation. The bottom three branches apply to ATC
translation.
3.6 MMU EFFECT ON AND
The following paragraphs describe MMU effects on the RSTI and MDIS pins.
3.6.1 Effect of on the MMUs
When the M68040 is reset by the assertion of the reset input signal, the E-bits of the TCR
and TTRs are cleared, disabling address translation. This reset causes logical addresses
to be passed through as physical addresses, allowing an operating system to set up the
translation tables and MMU registers as required. After the translation tables and registers
are initialized, the E-bit of the TCR can be set, enabling paged address translation. While
address translation is disabled, the attribute bits for an access that an ATC entry or a TTR
normally supplies are zero, selecting write-through cachable mode, no write protection,
and user page attribute bits cleared. RSTI does not affect the P-bit of the TCR.
A reset of the processor does not invalidate any entries in the ATCs or alter the page size.
A PFLUSH instruction must be executed to flush all existing valid entries from the ATCs
after a reset operation and before translation is enabled. PFLUSH can be executed even if
the E-bit is cleared.
3.6.2 Effect of on Address Translation
The assertion of MDIS prevents the MMUs from performing ATC searches and the
execution unit from performing table searches. With address translation disabled, logical
addresses are used as physical addresses. MDIS disables the MMUs on the next internal
access boundary when asserted and enables the MMUs on the next boundary after the
signal is negated. The assertion of this signal does not affect the operation of the
transparent translation registers or execution of the PFLUSH or PTEST instructions.
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