By appropriately configuring a TTR, flexible transparent mappings can be specified (refer
to 3.1.3 Transparent Translation Registers for field identification). For instance, to
transparently translate the user address space, the S-field is set to $0, and the logical
address mask is set to $FF in both an instruction and data TTR. To transparently translate
supervisor accesses of addresses $00000000–$0FFFFFFF with write protection, the
logical base address field is set to $0x, the logical address mask is set to $0F, the W-bit is
set to one, and the S-field is set to $1. The inclusion of independent TTRs in both the
instruction and data MMUs provides an exception to the merged instruction and data
address space, allowing different translations for instruction and operand accesses. Also,
since the instruction memory unit is only used for instruction prefetches, different
instruction and data TTRs can cause PC relative operand fetches to be translated
differently from instruction prefetches.
If either of the TTRs matched during an access to a memory unit (either instruction or
data), the access is transparently translated. If both registers match, the TT0 status bits
are used for the access. Transparent translation can also be implemented by the
translation tables of the translation tables if the physical addresses of pages are set equal
to their logical addresses.
The instruction and data MMUs process translations by first comparing the logical address
and privilege mode with the parameters of the TTRs. If there is a match, the MMU uses
the logical address as a physical address for the access. If there is no match, the MMU
compares the logical address and privilege mode with the tag portions of the entries in the
ATC and uses the corresponding physical address for the access when a match occurs.
When neither a TTR nor a valid ATC entry matches, the MMU initiates a table search
operation to obtain the corresponding physical address from the translation table. When a
table search is required, the processor suspends instruction execution activity and, at the
end of a successful table search, stores the address mapping in the appropriate ATC and
retries the access. The MMU creates a valid ATC entry for the logical address, and the
access is retried. If an access hits in the ATC but an access error or invalid page
descriptor was detected during the table search that created the ATC entry, the access is
aborted, and a bus error exception is taken.
If a write or read-modify-write access results in an ATC hit but the page is write protected,
the access is aborted, and an access error exception is taken. If the page is not write
protected and the modified bit of the ATC entry is clear, a table search proceeds to set the
modified bit in both the page descriptor in memory and in the ATC; the access is retried.
The ATC provides the address translation for the access if the modified bit of the ATC
entry is set for a write or read-modify-write access to an unprotected page, if the resident
bit is set (indicating the table search for the entry completed successfully), and if none of
the TTRs (instruction or data, as appropriate) match.
An ATC access error is not reported immediately, if the last 16 bits of a page is either an
A-line, illegal, CHK, or unimplemented instruction and the next page is non-resident.
Instead, the M68040 attempts to prefetch the next instruction on the missing page, then
the ATC access error exception is reported. The stacked PC points to the exceptional
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