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MOTOROLA M68040 USER'S MANUAL 3- 29
translation in the ATC and provides the physical address for the access, allowing the
memory unit to retry the original access.
There are some variations in the logical-to-physical mapping because of the two page
sizes. If the page size is 4 Kbytes, then logical address bit 12 is used to access the ATC's
memory, the tag comparators use bit 16, and physical address bit 12 is an ATC output. If
the page size is 8 Kbytes, then logical address bit 16 is used to access the ATC's
memory, and physical address bit 12 is driven by logical address bit 12. It is advisable that
a translation always be disabled before changing size and that the ATCs are flushed
before enabling translation again.
The M68040 is organized such that other operations always completely overlap the
translation time of the ATCs; thus, no performance penalty is associated with ATC
searches. The address translation occurs in parallel with indexing into the on-chip
instruction and data caches.
The MMU replaces an invalid entry when the ATC stores a new address translation. When
all entries in an ATC set are valid, the ATC selects a valid entry to be replaced, using a
pseudo-random replacement algorithm. A 2-bit counter, which is incremented for each
ATC access, points to the entry to replace when an access misses in the ATC. ATC hit
rates are application and page-size dependent, but hit rates ranging from 98% to greater
than 99% can be expected. These high rates are achieved because the ATCs are
relatively large (64 entries) and utilization efficiency is high with 8-Kbyte and 4-Kbyte page
sizes.
3.4 TRANSPARENT TRANSLATION
Four independent TTRs (DTT0 and DTT1 in the data MMU, ITT0 and ITT1 in the
instruction MMU) define four blocks of logical address space to be translated to physical
address space. These logical address spaces must be at least 16 Mbytes and can overlap
or be separate. Each TTR can be disabled and completely ignored. The following
description assumes that the TTRs are enabled.
When an MMU receives an address to be translated, the privilege mode and the eight
high-order bits of the address are compared to the logical address spaces defined by the
two TTRs for the corresponding MMU. The logical address space for each TTR is defined
by an S-field, logical base address field, and logical address mask field. The S-field allows
matching either user or supervisor accesses or both accesses. When a bit in the logical
address mask field is set, the corresponding bit of the logical base address is ignored in
the address comparison and privilege mode. Setting successively higher order bits in the
address mask increases the size of the physical address space.
The address for the current bus cycle and a TTR address match when the privilege mode
and logical base address bits are equal. Each TTR can specify write protection for the
block. When write protection is enabled for a block, write or read-modify-write accesses to
the block are aborted.
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