3- 28 M68040 USER'S MANUAL MOTOROLA
procedure ensures that the first write operation to a page sets the M-bit in both the ATC
and the page descriptor in the translation tables, even when a previous read operation
to the page had created an entry for that page in the ATC with the M-bit clear.
The upper bits of the translated physical address are contained in this field.
This bit is set if the table search successfully completes without encountering either a
nonresident page or a transfer error acknowledge during the search.
This bit identifies a pointer table or a page as a supervisor-only table or page. Only
programs operating in the supervisor privilege mode are allowed to access the portion
of the logical address space mapped by this descriptor when the S-bit is set. If the bit is
clear, both supervisor and user accesses are allowed.
U0, U1—User Page Attributes
These user-defined bits are not interpreted by the M68040. U0 and U1 are echoed to
the UPA0 and UPA1 signals, respectively, if an external bus transfer results from the
When set, this bit indicates the validity of the entry. This bit is set when the M68040
loads an entry. A flush operation by a PFLUSH or PFLUSHA instruction that selects this
entry clears the bit.
This write-protect bit is set when a W-bit is set in any of the descriptors encountered
during the table search for this entry. Setting a W-bit in a table descriptor write protects
all pages accessed with that descriptor. When the W-bit is set, a write access or a read-
modify-write access to the logical address corresponding to this entry causes an access
error exception to be taken immediately.
For each access to a memory unit, the MMU uses the four bits of the logical address
located just above the page offset (LA16–LA13 for 8K pages, LA15–LA12 for 4K pages) to
index into the ATC. The tags are compared with the remaining upper bits of the logical
address and FC2. If one of the tags matches and is valid, then the multiplexer choses the
corresponding entry to produce the physical address and status information. The ATC
outputs the corresponding physical address to the cache controller, which accesses the
data within the cache and/or requests an external bus cycle. Each ATC entry contains a
logical address, a physical address, and status bits.
When the ATC does not contain the translation for a logical address, a miss occurs. The
MMU aborts the current access and searches the translation tables in memory for the
correct translation. If the table search completes without any errors, the MMU stores the