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MOTOROLA M68040 USER'S MANUAL 3- 27
Each ATC entry consists of a physical address, attribute information from a corresponding
page descriptor, and a tag that contains a logical address and status information. Figure
3-21, which illustrates the entry and tag fields, is followed by field definitions listed in
alphabetical order.
U1 U0 S CM M W R PHYSICAL ADDRESS*
ENTRY
V G FC2 LOGICAL ADDRESS*
TAG
* For 4-Kbyte page sizes this field uses address bits 31–12; for 8-Kbyte page sizes, bits 31–13.
Figure 3-21. ATC Entry and Tag Fields
CM—Cache Mode
This field selects the cache mode and accesses serialization as follows:
00 = Cachable, Write-through
01 = Cachable, Copyback
10 = Noncachable, Serialized
11 = Noncachable
Section 4 Instruction and Data Caches provides detailed information on caching
modes, and Section 7 Bus Operation provides information on serialization.
FC2—Function Code Bit 2 (Supervisor/User)
This bit contains the function code corresponding to the logical address in this entry.
FC2 is set for supervisor mode accesses and cleared for user mode accesses.
G—Global
When set, this bit indicates the entry is global. Global entries are not invalidated by the
PFLUSH instruction variants that specify nonglobal entries, even when all other
selection criteria are satisfied.
Logical Address
This 13-bit field contains the most significant logical address bits for this entry. All 16
bits of this field are used in the comparison of this entry to an incoming logical address
when the page size is 4 Kbytes. For 8-Kbytes pages, the least significant bit of this field
is ignored.
M—Modified
The modified bit is set when a valid write access to the logical address corresponding to
the entry occurs. If the M-bit is clear and a write access to this logical address is
attempted, the M68040 suspends the access, initiates a table search to set the M-bit in
the page descriptor, and writes over the old ATC entry with the current page descriptor
information. The MMU then allows the original write access to be performed. This
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