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3- 16 M68040 USER'S MANUAL MOTOROLA
3.2.3 Translation Table Example
Figure 3-13 illustrates an access example to the logical address $76543210 while in the
supervisor mode with an 8-Kbyte memory page size. The RI field of the logical address,
$3B, is mapped into bits 8–2 of the SRP value to select a 32-bit root table descriptor at a
root-level table. The selected root table descriptor points to the base of a pointer-level
table, and the PI field of the logical address, $15, is mapped into bits 8–2 of this base
address to select a pointer descriptor within the table. This pointer table descriptor points
to the base of a page-level table, and the PGI field of the logical address, $1, is mapped
into bits 6–2 of this base address to select a page descriptor within the table.
3.2.4 Variations in Translation Table Structure
Several aspects of the MMU translation table structure are software configurable, allowing
the system designer flexibility to optimize the performance of the MMUs for a particular
system. The following paragraphs discuss the variations of the translation table structure.
3.2.4.1 INDIRECT ACTION. The M68040 provides the ability to replace an entry in a page
table with a pointer to an alternate entry. The indirection capability allows multiple tasks to
share a physical page while maintaining only a single set of history information for the
page (i.e., the modified indication is maintained only in the single descriptor). The
indirection capability also allows the page frame to appear at arbitrarily different addresses
in the logical address spaces of each task.
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