S—Supervisor Protection
This bit is set if the S-bit in the page descriptor is set. Setting this bit does not indicate
that a violation has occurred.
CM—Cache Mode
This 2-bit field is copied from the CM bits in the page descriptor.
This bit is set if the M-bit is set in the page descriptor associated with the address.
W—Write Protect
This bit is set if the W-bit is set in any of the descriptors encountered during the table
search. Setting this bit does not indicate that a violation has occurred.
T—Transparent Translation Register Hit
If the T-bit is set, then the PTEST address matches an instruction or data TTR, the R-bit
is set, and all other bits are zero.
The R-bit is set if the PTEST address matches an instruction or data TTR or if the table
search completes by obtaining a valid page descriptor.
The function of the MMUs is to translate logical addresses to physical addresses. The
MMUs perform translations according to control information in translation tables. The
operating system creates these translation tables and stores them in memory. The
processor then fetches a translation table as needed and stores it in an ATC.
3.2.1 Translation Tables
The M68040 uses the ATCs in the instruction and data memory units with translation
tables stored in memory to perform the translations from logical to physical addresses.
The operating system loads the translation tables for a program into memory. No
distinction is made in the translation of instruction accesses versus data accesses
because the instruction and data MMUs access the same translation table for a specific
privilege mode, either user or supervisor. This lack of distinction results in a merged
instruction and data address space.
Figure 3-7 illustrates the three-level tree structure of a general translation table supported
by the M68040. The root- and pointer-level tables contain the base addresses of the
tables at the next level. The page-level tables contain either the physical address for the
translation or a pointer to the memory location containing the physical address. Only a
portion of the translation table for the entire logical address space is required to be
resident in memory at any time—specifically, only the portion of the table that translates
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