MOTOROLA M68040 USER'S MANUAL 3- 5
3.1.3 Transparent Translation Registers
The data transparent translation registers (DTTR0 and DTTR1) and instruction
transparent translation registers (ITTR0 and ITTR1) are 32-bit registers that define blocks
of logical address space. The TTRs operate independently of the E-bit in the TCR and the
state of the MDIS signal. Data transfers to and from these registers are long-word
transfers. The TTR fields are defined following Figure 3-5, which illustrates TTR format.
Bits 12–10, 7, 4, 3, 1, and 0 always read as zero.
31 2423 161514131211109876543210
LOGICAL ADDRESS BASE LOGICAL ADDRESS MASK E S-FIELD 0 0 0 U1 U 0 0 C M 0 0 W 0 0
Figure 3-5. Transparent Translation Register Format
Logical Address Base
This 8-bit field is compared with address bits A31–A24. Addresses that match in this
comparison (and are otherwise eligible) are transparently translated.
Logical Address Mask
Since this 8-bit field contains a mask for the Logical Address Mask field, setting a bit in
this field causes the corresponding bit in the Logical Address Base field to be ignored.
Blocks of memory larger than 16 Mbytes can be transparently translated by setting
some of the logical address mask bits to ones. The low-order bits of this field can be set
to define contiguous blocks larger than 16 Mbytes.
This bit enables or disables transparent translation of the block defined by this register:
0 = Transparent translation disabled
1 = Transparent translation enabled
This field specifies the way FC2 is used in matching an address:
00 = Match only if FC2 = 0 (user mode access)
01 = Match only if FC2 = 1 (supervisor mode access)
1X = Ignore FC2 when matching
U0, U1—User Page Attributes
The user defines these bits, and the M68040 does not interpret them. U0 and U1 are
echoed to the UPA0 and UPA1 signals, respectively, if an external bus transfer results
from an access. These bits can be programmed by the user to support external
addressing, bus snooping, or other applications.