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MOTOROLA M68040 USER’S MANUAL 2- 7
procedure separates task-related supervisor activity from asynchronous, I/O-related
supervisor tasks that can only be coincidental to the currently executing task. The MSP
can separately maintain task control information for each currently executing user task,
and the software updates the MSP when a task switch is performed, providing an efficient
means for transferring task-related stack items. The value of the M-bit does not affect
execution of privileged instructions. Instructions that affect the M-bit are MOVE to SR,
ANDI to SR, EORI to SR, ORI to SR, and RTE. The processor automatically saves the M-
bit value and clears it in the SR as part of the exception processing for interrupts.
2.2.2.2 STATUS REGISTER. The SR (see Figure 2-5) stores the processor status. In the
supervisor mode, software can access the full SR, including the CCR available in user
mode (see 2.2.1.5 Condition Code Register) and the interrupt priority mask and
additional control bits available only in the supervisor mode. These bits indicate the
following states for the processor: one of two trace modes (T1, T0), supervisor or user
mode (S), and master or interrupt mode (M).
The term SSP refers to the ISP and MSP. The M and S bits of the SR decide which SSP
to use. When the S-bit is one and the M-bit is zero, the ISP is the active stack pointer;
when the S-bit is one and the M-bit is one, the MSP is the active stack pointer. The ISP is
the default mode after reset and corresponds to the MC68000, MC68008, MC68010, and
CPU32 supervisor mode.
T1 T0 S M 0 I2 I1 I0 X N Z V C000
SYSTEM BYTE
USER BYTE
(CONDITION CODE REGISTER)
TRACE
ENABLE
INTERRUPT
PRIORITY MASK
SUPERVISOR/USER STATE
MASTER/INTERRUPT STATE EXTEND
NEGATIVE
ZERO
OVERFLOW
CARRY
15 14 13 12 11 10 9 8 7 56 43210
Figure 2-5. Status Register
2.2.2.3 VECTOR BASE REGISTER. The VBR contains the base address of the exception
vector table in memory. The displacement of an exception vector is added to the value in
this register to access the vector table. Refer to Section 8 Exception Processing for
information on exception vectors.
2.2.2.4 ALTERNATE FUNCTION CODE REGISTERS. The alternate function code
registers contain 3-bit function codes. Function codes can be considered extensions of the
32-bit logical address that optionally provides as many as eight 4-Gbyte address spaces.
The processor automatically generates function codes to select address spaces for data
and programs at the user and supervisor modes. Certain instructions use the SFC and
DFC registers to specify the function codes for operations.
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