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MOTOROLA M68040 USER’S MANUAL 2- 3
effective address. Also, some instructions access multiple memory operands and initiate
fetches for each operand.
The instruction finishes execution in the execute stage. Instructions with write-back
operands to memory generate pending write accesses that are passed to the write-back
stage. The write occurs to the data memory unit if it is not busy. If the following instruction,
which is in the <ea> fetch stage, requires an operand fetch, the write-back stalls in the
write-back stage since it is at a lower priority. The write-back can stall indefinitely until
either the data memory unit is free or another write is pending from the execution stage.
Figure 2-2 illustrates a write cycle, which begins in the IU pipeline. The IU stores the
logical address and data for a write operation in a temporary holding register (WB3). Write
operation control passes from the IU to the data memory unit once the data memory unit
is idle. When the data memory unit receives the logical address and data from the IU, it
stores the logical address and data to a second temporary holding register (WB2). The
data memory unit then translates the logical address into a physical address. If the
address translation is successful, the data memory unit either stores an address
translation in the data cache (write hit) or passes it to the bus controller (write-through with
write miss). Once the bus controller is ready to execute the external write operation, it
multiplexes the data to the correct data byte lanes and stores the multiplexed data and
physical address into a third holding register (WB1). WB1 is used in the actual write
operation seen on the address and data buses. Appendix B MC68EC040 contains details
on address translation in the MC68EC040.
DECODE
<ea>
CALCULATE
WRITE-
BACK (WB3)
INTEGER UNIT
INSTRUCTION MEMORY UNIT
INSTRUCTION
FETCH
EXECUTE
<ea>
FETCH
ADDRESS
BUS
DATA
BUS
DATA CACHE
BUS
CONTROLLER
WB1
DATA
ATC
DATA MEMORY UNIT
DATA MMU/
CACHE/SNOOP
CONTROLLER
WB2
DATA MUX
PUSH
BUFFER
BUS
CONTROL
SIGNALS
LOGICAL ADDRESS
PHYSICAL ADDRESS
Figure 2-2. Write-Back Cycle Block Diagram
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