Loading...
INDEX-4 M68040 USER’S MANUAL MOTOROLA
Instructions
Forced Rounding Precision, 9-13, 9-31, 9-34
Privilege Violation Generating, 8-10
Trace Exception Generating, 8-10
Integer Unit, 1-4, 2-1, 7-3
Supervisor Programming Model, 1-7, 2-5, 2-6
User Programming Model, 1-6, 2-4
Integer Unit Pipeline, 1-3, 2-1–2-3, 10-5
<ea> Calculate Stage, 1-3, 2-1, 2-2, 10-3,
10-4, 10-6
<ea> Fetch Stage, 1-3, 2-1, 2-2, 2-3, 7-4, 10-3
Decode Stage, 2-1, 2-2
Execute Stage, 2-2, 5-12, 8-1, 8-7, 10-3, 10-4,
10-6
Write-Back Stage, 7-43, 10-4,
see also
Write-
Backs
Integer Unit Registers
Address Registers, 1-8, 2-4
Cache Control Register (CACR), 1-8, 2-8, 4-5,
8-17
Condition Code Register (CCR), 1-8, 2-5;
X-Bit, 2-5
Data Registers, 2-4
Function Code Registers, 1-8, 2-7
Index Registers, 1-8
Interrupt Stack Pointer (ISP), 8-4
Program Counter (PC), 1-8, 2-5, 8-4
Stack Pointer (SP), 1-8, 2-5; Supervisor, 2-6
Status Register (SR), 2-7, 8-2
S-Bit, 1-5
M-Bit, 2-6, 2-7, 8-4
I-Bits, 7-29, 8-13
Vector Base Register (VBR), 1-8, 2-7, 8-4,
8-17
Intermediate Result, 9-11, 9-13, 9-15, 9-16, 9-21,
9-31, 9-33, 9-37; Format, 9-12
Interrupt Exceptions, 5-14, 7-29, 7-31, 8-12, 8-20
Interrupts, 1-5
Acknowledged Bus Cycle, 5-12, 7-29–7-35,
7-31, 8-2
Pending Procedure, 7-30
Priority Level, 5-11
Priority Mask, 7-29, 8-2
Request, 8-13
Vector Numbers, 8-15
–J–
JTAG (IEEE Standard 1149.1), 5-15, 6-1
Boundary Scan Control, 6-6, 6-9
BSDL Description, 6-15
Disabling, 6-13
Electrical And Timing Specifications, 11-1
Instructions,
see
JTAG Instructions
JTAG Instructions
BYPASS, 6-3
DRVCTL.T, 6-3, 6-12
EXTEST, 6-3, 6-12
HI-Z, 6-3, 6-12
PRIVATE, 6-3
SAMPLE/PRELOAD, 6-3
SHUTDOWN, 6-3, 6-12
JTAG Output Drivers, 6-4, 6-5
JTAG Registers
Boundary Scan Data Register, 6-2, 6-4, 6-5,
6-13
Instruction Shift Register, 6-2–6-6
Test Data Register, 6-3, 6-2
JTAG Scan, A-5, B-5
Output Drivers, 6-4, 6-5
Registers,
see
JTAG Registers
System Clock Restriction, 6-3
TAP Controller, 6-1, 6-2, 6-6, 6-13
Junction Temperature, 11-29, 11-30
–L–
Line Filling, 7-6, 7-12, 7-13
Line Bus Cycles,
see
Bus Cycles
Locked Bus Cycles,
see
Bus Cycles
Logical Address, 2-3, 2-7, 3-29, 4-3, 3-2, 3-4
Format, 3-8
Space, 1-8; Defined 3-29
–M–
M68040FPSP Exception Handler, 9-23
BSUN, 9-26
OPERR, 9-30
OVFL, 9-31, 9-32
SNAN, 9-27, 9-28
Unimplemented Instruction, 9-35, 9-38
Loading...
Terms of Use | Privacy Policy | DMCA Policy
2006-2020 Rsmanuals.com