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2- 2 M68040 USER’S MANUAL MOTOROLA
INSTRUCTION DATA
FROM CACHE OR BUS
CONTROLLER
TO FPU
<ea> CALCULATE
<ea> FETCH TO CACHE OR
BUS CONTROLLER
EXECUTE
WRITE-BACK
SHADOW
SHADOW
INSTRUCTION
FETCH
DECODE
TO CACHE OR
BUS CONTROLLER
Figure 2-1. Integer Unit Pipeline
An instruction stream is fetched from the instruction memory unit and decoded on an
instruction-by-instruction basis in the decode stage. Multiple instructions are fetched to
keep the pipeline stages full so that the pipeline will not stall.
The decoded instruction is then passed to the <ea> calculate stage to calculate the
effective addresses that the instruction requires. The <ea> calculate stage initiates
additional fetches from the instruction stream to obtain the effective address extension
words and performs the effective address calculation. The initial execution of the
instruction in the execute stage handles any data registers required for the calculation,
which passes the register back to the <ea> calculate stage.
The resulting effective address is passed to the <ea> fetch stage, which initiates an
operand fetch from the data memory controller if the effective address is for a source
operand. The fetched operand is returned to the execute stage, which completes
execution of the instruction and writes any result to either a data register, memory, or back
to the <ea> calculate stage for storage in an address register. For a memory destination,
the <ea> fetch stage passes the address to the execution stage.
The previously described sequence of effective address calculation and fetch can occur
multiple times for an instruction, depending on the source and/or destination addressing
modes. For memory indirect addressing modes, the <ea> calculate stage initiates an
operand fetch from the intermediate indirect memory address, then calculates the final
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