MOTOROLA M68040 USER’S MANUAL 2- 1
This section describes the organization of the M68040 integer unit (IU) and presents a
brief description of the associated registers. Refer to Section 3 Memory Management
Unit (Except MC68EC040 and MC68EC040V) for details concerning the memory
management unit (MMU) programming model, and to Section 9 Floating-Point Unit
(MC68040 Only) for details concerning the floating-point unit (FPU) programming model.
2.1 INTEGER UNIT PIPELINE
The IU carries out logical and arithmetic operations using six separate subunits. Each unit
is dedicated to a different stage of the IU pipeline, handling a total of six separate
instructions simultaneously. Pipelining is a technique that overlaps the processing of
different parts of several instructions. Pipelining simulates an assembly line with the IU
containing a number of instructions in different phases of processing. The IU pipeline
consists of six stages:
1. Instruction Fetch—Fetching an instruction from memory.
2. Decode—Converting an instruction into micro-instructions.
3. <ea> Calculate—If the instruction calls for data from memory, the location of the
data, its memory address is calculated.
4. <ea> Fetch—Data is fetched from memory.
5. Execute—The data is manipulated during execution.
6. Write-Back—The result of the computation is written back to on-chip caches or
The pipeline contains special shadow registers that can begin processing future
instructions for conditional branches while the main pipeline is processing current
instructions. The <ea> calculate stage eliminates pipeline blockage for instructions with
postincrement, postdecrement, or immediate add and load to address register for updates
that occur in the <ea> calculate stage. The write-back stage can write data over the
system bus to store a result in external memory or directly to on-chip caches. These write-
backs to memory can be deferred until the most opportune moment because of the
M68040 bus interface. Figure 2-1 illustrates the IU pipeline.