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MOTOROLA M68040 USER’S MANUAL C- 23
C.7.7 Input AC Timing Specifications (See Figures C-13 to C-21)
PRELIMINARY
0–16.67 MHz 25 MHz 33 MHz
Num Characteristic Min Max Min Max Min Max Unit
15 Data-In Valid to BCLK (Setup) 5 5 4 ns
16 BCLK to Data-In Invalid (Hold) 4 4 4 ns
17 BCLK to Data-In High Impedance (Read
Followed by Write) 49 49 — 36.5 ns
22a TA Valid to BCLK (Setup) 10 10 10 ns
22b TEA Valid to BCLK (Setup) 10 10 10 ns
22c TCI Valid to BCLK (Setup) 10 10 10 ns
22d TBI Valid to BCLK (Setup) 11 11 10 ns
23 BCLK to TA, TEA, TCI, TBI Invalid (Hold) 2 2 2 ns
24 AVEC Valid to BCLK (Setup) 5 5 5 ns
25 BCLK to AVEC Invalid (Hold) 2 2 2 ns
41a BB Valid to BCLK (Setup) 7 7 7 ns
41b BG Valid to BCLK (Setup) 8 8 7 ns
41c CDIS, MDIS* Valid to BCLK (Setup) 10 10 8 ns
41d IPL≈ Valid to BCLK (Setup) 4 4 3 ns
42 BCLK to BB, BG, CDIS, MDIS*, IPL≈ Invalid
(Hold) 2 2 2 ns
44a Address Valid to BCLK (Setup) 8 8 7 ns
44b SIZx Valid to BCLK (Setup) 12 12 8 ns
44c TTx Valid to BCLK (Setup) 6 6 8.5 ns
44d R/W Valid to BCLK (Setup) 6 6 5 ns
44e SCx Valid to BCLK (Setup) 10 10 11 ns
45 BCLK to Address SIZx, TTx, R/W, SCx
Invalid (Hold) 2 2 2 ns
46 TS Valid to BCLK (Setup) 5 5 9 ns
47 BCLK to TS Invalid (Hold) 2 2 2 ns
49 BCLK to BB High Impedance
(Processor Assumes Bus Mastership) — 9— 9 —9ns
51 RSTI Valid to BCLK 5 5 4 ns
52 BCLK to RSTI Invalid 2 2 2 ns
BLFO change to valid IPL≈, RSTI (setup) 5 — 5 5 ns
DIPEND valid to IPL≈ invalid (Hold) 0 0 0 ns
VRSTI pulse width, leaving LPSTOP mode 10 10 10 ns
ZIPL≈, RSTI valid to LFO change (Hold) 500 500 500 ns
NOTE: *Not on the MC68EC040V.
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