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C- 22 M68040 USER’S MANUAL MOTOROLA
C.7.6 Output AC Timing Specifications (see Figures C-13* to C-21)
PRELIMIINARY
0–16.67 MHz 25 MHz 33 MHz
Num Characteristic Min Max Min Max Min Max Unit
11 BCLK to Address, CIOUT, LOCK, LOCKE,
PSTx, R/W, SIZx, TLNx, TMx, TTx, UPAx
Valid
9 30 9 30 6.5 25 ns
12 BCLK to Output Invalid (Output Hold) 9 9 6.5 ns
13 BCLK to TS Valid 9 30 9 30 6.5 25 ns
14 BCLK to TIP Valid 9 30 9 30 6.5 25 ns
18 BCLK to Data-Out Valid 9 32 9 32 6.5 27 ns
19 BCLK to Data-Out Invalid (Output Hold) 9 9 6.5 ns
20 BCLK to Output Low Impedance 9 9 6.5 ns
21 BCLK to Data-Out High Impedance 9 20 9 20 6.5 17 ns
38 BCLK to Address, CIOUT, LOCK, LOCKE ,
R/W , SIZx, TS, TLNx, TMx, TTx, UPAx High
Impedance
9 18 9 18 6.5 15 ns
39 BCLK to BB, TA, TIP High Impedance 19 28 19 28 14 25 ns
40 BCLK to BR , BB Valid 9 30 9 30 6.5 23 ns
43 BCLK to MI Valid 9 30 9 30 6.5 25 ns
48 BCLK to TA Valid 9 30 9 30 6.5 25 ns
50 BCLK to IPEND, PSTx, RSTO Valid 9 30 9 30 6.5 25 ns
WRSTI active to SCD inactive. 8 100 8 100 8 100 ns
AIPL≈ to SCD invalid 8 100 8 100 8 100 ns
NOTE:
* Output timing is specified for a valid signal measured at the pin. Timing is specified driving an unterminated
30- transmission line with a length characterized by a 2.5-ns one-way propagation delay. Buffer output
impedance is typically 30 ; the buffer specifications include approximately 5 ns for the signal to propagate
the length of the transmission line and back.
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