The MC68040V and MC68EC040V include dedicated user-accessible test logic that is
fully compatible with the IEEE standard 1149.1A
Standard Test Access Port and
Boundary Scan Architecture
. Problems associated with testing high-density circuit boards
have led to the standard’s development under the sponsorship of the IEEE Test
Technology Committee and the Joint Test Action Group (JTAG).
The following paragraphs are to be used in conjunction with the supporting IEEE
document and includes those chip-specific items that the IEEE standard requires to be
defined and additional information specific to the MC68040V and MC68EC040V
implementations. For example, the IEEE standard 1149.1A test access port (TAP)
controller states are referenced in this section but are not described. For these details and
application information regarding the standard, refer to the IEEE standard 1149.1A
The MC68040V and MC68EC040V implementations support circuit board test strategies
based on the standard. The test logic utilizes static logic design and is system logic
independent of the device. The MC68040V and MC68EC040V implementations provide
capabilities to:
a. Perform boundary scan operations to test circuit board electrical continuity,
b. Bypass the MC68040V and MC68EC040V by reducing the shift register path to a
single cell,
c. Sample the MC68040V and MC68EC040V system pins during operation and
transparently shift out the result,
d. Disable the output drive to output-only pins during circuit board testing.
The IEEE standard 1149.1A test logic cannot be considered
completely benign to those planning not to use this capability.
Certain precautions must be observed to ensure that this logic
does not interfere with system operation. Refer to C.6.4
Disabling The IEEE Standard 1149.1A Operation.
Figure C-4 illustrates a block diagram of the MC68040V and MC68EC040V
implementations of IEEE standard 1149.1A. The test logic includes a 16-state dedicated
TAP controller. These 16 controller states are defined in detail in the IEEE standard
1149.1A, but only 8 are included in this section.
Test-Logic-Reset Run-Test/Idle
Capture-IR Capture-DR
Update-IR Update-DR
Shift-IR Shift-DR
Four dedicated signal pins provides access to the TAP controller:
TCK—A test clock input that synchronizes the test logic.
TMS—A test mode select input with an internal pullup resistor sampled on the rising
edge of TCK to sequence the TAP controller.
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