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MOTOROLA M68040 USER’S MANUAL C- 7
C.3 CLOCKING DURING NORMAL OPERATION
During normal operation of the processor, the BCLK should be driven with a 50% (±5%)
duty cycle (refer to C.7 MC68040V and MC68EC040V Electrical Characteristics for
details). The frequency of BCLK can not be changed during normal operation. Altering the
BCLK frequency during normal operation (the LFO signal is negated) will result in
unspecified operation. In the event that the BCLK input is lost, a processor reset is
required. Once the loss of BCLK is detected during normal operation, the processor
asserts LOC, indicating a loss of clock. External logic can then reset the processor to
resume normal operation.
C.4 RESET OPERATION
An external device asserts the RSTI to reset the processor. When power is applied to the
system, external circuitry should assert RSTI for a minimum of 10 BCLK cycles after VCC
is within tolerance. Figure C-2 is a functional timing diagram of the power-on reset
operation, illustrating the relationships among VCC, RSTI, and bus signals. The BCLK
signal is required to be stable by the time RSTI is negated. The VIH levels of any pin must
not exceed VCC + 2.5V. RSTI is internally synchronized for two BCLKs before being used
and must meet the specified setup and hold times to BCLK (specifications #51 and #52 in
C.7 MC68040V and MC68EC040V Electrical Characteristics) only if recognition by a
specific BCLK rising edge is required. MI is asserted while the MC68040V is in reset.
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