3. Orderly shutdown of the clock circuitry, culminating in the low-power stop mode.
4. Return to normal operation after the receipt of a non-masked interrupt or reset when
the clocks are restarted in an orderly manner.
Once the LPSTOP instruction has reached the execute stage of the IU pipeline and when
all CPU and bus activity has completed, the IU generates an LPSTOP broadcast cycle.
Table C-2 lists how the LPSTOP broadcast cycle drives the bus.
Table C-2. Bus Encodings During
LPSTOP Broadcast Cycle
Signals Encoding Signals Encoding
TT1, TT0 $3 D31–D16 $XXXX
TM2–TM0 $0 D15–D0 #<data>
SIZ1, SIZ0 $2
Either TA or TEA terminates the LPSTOP broadcast cycle. By withholding the assertion of
TA or TEA, external logic can extend the cycle, controlling the beginning of the low-power
stop mode. During this extension, the processor is ready for bus arbitration.
Upon termination of the LPSTOP broadcast cycle, the status register (SR) is updated with
the data portion of the immediate operand (updating the interrupt priority mask level). The
IU updates the processor status lines PST3–PST0 with the new status code of $6 and
halts. Then, SCD is asserted signaling the beginning of the low-power stop mode. All
instructions in the integer unit pipeline that followed LPSTOP remain in the pipeline during
the low-power stop mode.
The processor stays in the low-power stop mode until a non-masked interrupt or reset
exception occurs. A non-masked interrupt exception is defined as a higher priority than the
value in the interrupt priority mask bits of the SR, while holding the interrupt priority level
(IPL≈) lines until IPEND is asserted. IPL≈ are used in the low-power stop mode to restart
the clocks and return the processor to normal operation. If an interrupt request has a
priority higher than the value in the interrupt priority mask bits of the SR, the clock control
logic negates SCD and restarts the PLL. If the pending interrupt has a lower priority than
the interrupt priority mask bits, the clock logic doesn't restart the PLL and the processor
will not resume normal operation. The MC68040V and MC68EC040V will enter low-power
mode regardless of any interrupts that are pending once the LPSTOP instruction starts.
Once the clock control logic negates SCD and the PLL is restarted, a valid BCLK must be
provided to the processor. When the clocks are phase locked, an interrupt, a bus error, or
a reset exception begins. The interrupt exception forces all instructions in the pipeline to
be aborted that have not reached the execute stage; while the reset exception aborts any
processing in progress (pre-fetched instructions prior to entering low-power stop mode)
and cannot be recovered.
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