MOTOROLA M68040 USER’S MANUAL B- 9
Once RSTI is negated, the processor is internally held in reset for another 128 clock
cycles. During the reset period, all three-statable signals are three-stated, and the rest are
driven to their inactive state. Once the internal reset signal negates, all bus signals remain
in a high-impedance state until the processor is granted the bus. After this, the first bus
cycle for reset exception processing begins. In Figure B-6, the processor assumes implicit
ownership of the bus before the first bus cycle begins. The levels on the CDIS, JS1 (MDIS
on the MC68040), and IPL2–IPL0 signals are not sampled when RSTI is negated.
For processor resets after the initial power-on reset, RSTI should be asserted for at least
10 clock periods. Figure B-6 illustrates timing associated with a reset when the processor
is executing bus cycles. Note that BB and TIP (and TA driven during a snooped access)
are asserted before transitioning to a three-state level. Processor reset causes any bus
cycle in progress to terminate as if TA or TEA had been asserted. Also, the processor
initializes registers appropriately for a reset exception.
Figure B-6. MC68EC040 Normal Reset Timing
When a RESET instruction is executed, the processor drives the reset out (RSTO) signal
for 512 BCLK cycles. In this case, the processor resets the external devices of the system,
and the internal registers of the processor are unaffected. The external devices connected
to RSTO are reset at the completion of the RESET instruction. An RSTI signal that is
asserted to the processor during execution of a RESET instruction immediately resets the
processor and causes RSTO to negate. RTSO can be logically ANDed with the external
signal driving RTSI to derive a system reset signal that is asserted for both an external
processor reset and execution of a RESET instruction.